公开(公告)号：US06668334B1

公开(公告)日：2003-12-23

申请号：US09604842

申请日：2000-06-27

申请人： Christopher John Abel ,  Angelo Rocco Mastrocola ,  Douglas Edward Sherry ,  William Burdett Wilson

发明人： Christopher John Abel ,  Angelo Rocco Mastrocola ,  Douglas Edward Sherry ,  William Burdett Wilson

IPC分类号： G06F104

CPC分类号： H03K5/19 ,  G01R31/31725 ,  H03K5/1515 ,  H04L7/0083

摘要： A loss-of-clock (LOC) detector circuit detects a clock failure substantially within a specified number of clock periods and generates a loss-of-clock signal. The LOC detector includes a frequency-to-current converter which generates a charging current substantially proportional to a frequency of an input clock. A capacitor accepts the charging current and provides a terminal voltage that changes in response to the charging current. An edge detector receives the input clock signal as an input and produces an output pulse on an edge of the input clock signal. A switch is coupled to the capacitor such that the capacitor is discharged to a reference potential when the switch is closed. The switch is controlled by the edge detector to close when the edge detector output pulse is asserted. A comparator generates a loss-of-clock signal when the voltage on the capacitor passes a trip voltage of the comparator.

摘要翻译： 时钟（LOC）检测器电路基本上在指定数量的时钟周期内检测时钟故障，并产生时钟损失信号。 LOC检测器包括频率到电流转换器，其产生基本上与输入时钟的频率成比例的充电电流。 电容器接受充电电流并提供响应于充电电流而改变的端电压。 边缘检测器接收输入时钟信号作为输入，并在输入时钟信号的边沿产生输出脉冲。 开关耦合到电容器，使得当开关闭合时，电容器被放电到参考电位。 当边缘检测器输出脉冲被置位时，开关由边沿检测器控制。 当电容器上的电压通过比较器的跳闸电压时，比较器产生时钟损失信号。

公开(公告)号：US5862187A

公开(公告)日：1999-01-19

申请号：US509563

申请日：1995-07-31

申请人： Mirmira Ramarao Dwarakanath ,  Kadaba R. Lakshmikumar ,  Angelo Rocco Mastrocola ,  Krishnaswamy Nagaraj ,  Douglas Edward Sherry

发明人： Mirmira Ramarao Dwarakanath ,  Kadaba R. Lakshmikumar ,  Angelo Rocco Mastrocola ,  Krishnaswamy Nagaraj ,  Douglas Edward Sherry

IPC分类号： H04L27/22 ,  H04L27/233

CPC分类号： H04L27/2338

摘要： A receiver for decoding passband signal pulses transmitted in accordance with a M-ARY phase shift keying modulation scheme, comprises a multiphase sampler for sampling received passband signal pulses in the passband frequency range so as to generate a plurality of digital words corresponding to the sampled passband signal pulses, such that each digital word represents the phase of each sampled passband signal pulse. A phase reference register or other storage device is coupled to the multiphase sampler for storing one of the digital words as a phase reference such that other digital words generated by the multiphase sampler are compared with the digital word corresponding to the phase reference for decoding the passband signal pulses.

摘要翻译： 用于解码根据M-ARY相移键控调制方案发送的通带信号脉冲的接收机包括用于在通带频率范围中对接收的通带信号脉冲进行采样的多相采样器，以产生对应于采样通带的多个数字字 信号脉冲，使得每个数字字表示每个采样的通带信号脉冲的相位。 相位参考寄存器或其他存储装置耦合到多相采样器，用于将数字字中的一个存储为相位参考，使得由多相采样器产生的其他数字字与对应于相位参考的数字字进行比较，以解码通带 信号脉冲。