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1.发明授权Apparatus for detecting clock failure within a fixed number of cycles of the clock 有权用于在时钟的固定周期内检测时钟故障的装置公开(公告)号：US06668334B1
公开(公告)日：2003-12-23
申请号：US09604842
申请日：2000-06-27
申请人： Christopher John Abel , Angelo Rocco Mastrocola , Douglas Edward Sherry , William Burdett Wilson
发明人： Christopher John Abel , Angelo Rocco Mastrocola , Douglas Edward Sherry , William Burdett Wilson
IPC分类号： G06F104
CPC分类号： H03K5/19 , G01R31/31725 , H03K5/1515 , H04L7/0083
摘要： A loss-of-clock (LOC) detector circuit detects a clock failure substantially within a specified number of clock periods and generates a loss-of-clock signal. The LOC detector includes a frequency-to-current converter which generates a charging current substantially proportional to a frequency of an input clock. A capacitor accepts the charging current and provides a terminal voltage that changes in response to the charging current. An edge detector receives the input clock signal as an input and produces an output pulse on an edge of the input clock signal. A switch is coupled to the capacitor such that the capacitor is discharged to a reference potential when the switch is closed. The switch is controlled by the edge detector to close when the edge detector output pulse is asserted. A comparator generates a loss-of-clock signal when the voltage on the capacitor passes a trip voltage of the comparator.
摘要翻译： 时钟（LOC）检测器电路基本上在指定数量的时钟周期内检测时钟故障，并产生时钟损失信号。 LOC检测器包括频率到电流转换器，其产生基本上与输入时钟的频率成比例的充电电流。 电容器接受充电电流并提供响应于充电电流而改变的端电压。 边缘检测器接收输入时钟信号作为输入，并在输入时钟信号的边沿产生输出脉冲。 开关耦合到电容器，使得当开关闭合时，电容器被放电到参考电位。 当边缘检测器输出脉冲被置位时，开关由边沿检测器控制。 当电容器上的电压通过比较器的跳闸电压时，比较器产生时钟损失信号。
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公开(公告)号：US20140077850A1
公开(公告)日：2014-03-20
申请号：US13528951
申请日：2012-06-21
IPC分类号： H03L7/08
CPC分类号： H03L7/08 , H03L7/0805 , H03L7/0816
摘要： In one embodiment, a delay-locked loop (DLL) for synchronizing a phase of a periodic digital output signal with a phase of a periodic digital input signal includes a deskew element responsive to the periodic digital input signal to the DLL and the periodic digital output signal from the DLL for suppressing jitter in the periodic digital output signal by synchronizing transitions in the periodic digital output signal with transitions in the periodic digital input signal and generating a final jitter-suppressed periodic digital output signal.
摘要翻译： 在一个实施例中，用于将周期性数字输出信号的相位与周期性数字输入信号的相位同步的延迟锁定环路（DLL）包括响应于DLL的周期性数字输入信号和周期性数字输出的去偏移元件 来自DLL的信号，用于通过使周期性数字输出信号中的转变与周期性数字输入信号中的跃迁同步并产生最终抖动抑制的周期性数字输出信号来抑制周期性数字输出信号中的抖动。
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公开(公告)号：US06037621A
公开(公告)日：2000-03-14
申请号：US126032
申请日：1998-07-29
IPC分类号： H01L23/522 , H01L29/72
CPC分类号： H01L23/5223 , H01L2924/0002
摘要： An on-chip capacitor structure comprising a lower metal layer and an upper metal layer; an array of metal islands disposed between the lower and the upper metal layers; each island of the array of islands being electrically connected to either the lower layer or the upper layer such that no two adjacent islands are connected to the same layer.
摘要翻译： 一种片上电容器结构，包括下金属层和上金属层; 布置在下金属层和上金属层之间的金属岛阵列; 岛阵列的每个岛电连接到下层或上层，使得没有两个相邻的岛连接到相同的层。
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公开(公告)号：US09007106B2
公开(公告)日：2015-04-14
申请号：US13528951
申请日：2012-06-21
CPC分类号： H03L7/08 , H03L7/0805 , H03L7/0816
摘要： In one embodiment, a delay-locked loop (DLL) for synchronizing a phase of a periodic digital output signal with a phase of a periodic digital input signal includes a deskew element responsive to the periodic digital input signal to the DLL and the periodic digital output signal from the DLL for suppressing jitter in the periodic digital output signal by synchronizing transitions in the periodic digital output signal with transitions in the periodic digital input signal and generating a final jitter-suppressed periodic digital output signal.
摘要翻译： 在一个实施例中，用于将周期性数字输出信号的相位与周期性数字输入信号的相位同步的延迟锁定环路（DLL）包括响应于DLL的周期性数字输入信号和周期性数字输出的去偏移元件 来自DLL的信号，用于通过使周期性数字输出信号中的转变与周期性数字输入信号中的跃迁同步并产生最终抖动抑制的周期性数字输出信号来抑制周期性数字输出信号中的抖动。
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5.发明授权Digital data receivers, methods and circuitry for differentiating between transmitted signals of varying physical protocols and frequencies 失效用于区分不同物理协议和频率的发射信号之间的数字数据接收机，方法和电路
公开(公告)号：US5717720A
公开(公告)日：1998-02-10
申请号：US355366
申请日：1994-12-13
CPC分类号： H04L12/44 , H04L25/0262 , H04L29/06 , H04L69/18
摘要： Disclosed are digital data receivers, methods and circuitry for differentiating between signals and data packets of varying physical layer protocols and frequencies transferred over a digital burst mode communications system, such as a packet-based LAN. Transitions in a received input signal to a squelch circuit start a counter which asserts one or more signals at various predetermined times from the transition. The absence or presence of the signal when the next transition in the input signal occurs indicates whether the input signal is less than or greater than a frequency associated with a particular predetermined time interval. When a predetermined number of transitions meeting a particular frequency requirement are received, the input signal is determined to be received at a particular frequency.
摘要翻译： 公开了用于区分不同物理层协议的信号和数据分组之间的数字数据接收机，方法和电路，以及通过数字突发模式通信系统（诸如基于分组的LAN）传送的频率。 接收到的输入信号到静噪电路的转换开始一个计数器，该计数器从转换的各种预定时间断言一个或多个信号。 当输入信号中的下一转换发生时，信号的不存在或不存在指示输入信号是否小于或大于与特定预定时间间隔相关联的频率。 当接收到满足特定频率要求的预定数量的转换时，确定输入信号以特定频率被接收。
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