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公开(公告)号：US5912589A
公开(公告)日：1999-06-15
申请号：US883007
申请日：1997-06-26
IPC分类号： H03F3/45
CPC分类号： H03F3/4508 , H03F3/45085 , H03F3/45278 , H03F2203/45286 , H03F2203/45456 , H03F2203/45466 , H03F2203/45471 , H03F2203/45476 , H03F2203/45508
摘要： A circuit for stabilizing the gain-bandwidth product of analog circuits containing bipolar devices which determine the gm is disclosed. The stabilization circuit is formed to generate a reference current that is proportional to a reference capacitance C.sub.S and the thermal voltage V.sub.T. The reference current is ultimately mirrored (as the bias current) into the bipolar devices which determine the gm within the analog circuit. Since the transconductance gm of a bipolar device can be expressed as collector current, I.sub.C, divided by V.sub.T, the thermal voltage factor of the bias current itself will "cancel" the thermal voltage factor present in the transconductance. The effects related to the remaining variable, the capacitance, will be eliminated as long as the reference capacitance is formed to "track" the analog circuit capacitance by using similar types of capacitance to implement both capacitors and forming both the stabilization circuit and the analog circuit on the same silicon chip. The stabilization circuit can be constructed in modular form and may include a module capable of creating a stabilized RC time constant that is likewise unchanged by variations in temperature or processing.
摘要翻译： 公开了一种用于稳定包含确定gm的双极器件的模拟电路的增益带宽乘积的电路。 形成稳定电路以产生与参考电容CS和热电压VT成比例的参考电流。 最终将参考电流镜像（作为偏置电流）进入确定模拟电路内的gm的双极型器件。 由于双极器件的跨导gm可以表示为集电极电流（IC）除以VT，因此偏置电流本身的热电压系数将“抵消”跨导中存在的热电压系数。 只要参考电容形成为“跟踪”模拟电路电容，通过使用相似类型的电容来实现两个电容并形成稳定电路和模拟电路两者，就可以消除与剩余变量相关的影响，即电容。 在同一个硅芯片上。 稳定电路可以以模块化形式构造，并且可以包括能够产生稳定的RC时间常数的模块，其通过温度或处理的变化同样不变。
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公开(公告)号：US5847576A
公开(公告)日：1998-12-08
申请号：US746261
申请日：1996-11-07
IPC分类号： H03K19/00 , H03K19/003 , H03K19/082 , H03K19/094 , H03K19/20
CPC分类号： H03K19/0027 , H03K19/0013
摘要： A logic gate arrangement having a master gate or section for controlling the logic threshold voltage of slave gates responsive to the master. Both the master and slave gates have two opposite conductivity type transistors disposed in combination with a logic function circuit. The transistors have a common gate connection to a control input. Varying the voltage on the control input varies the logic threshold voltage of the gate. The logic function in the master gate is typically an inverter, with input and output connected together and driving the control inputs of the slave gates. The logic function of the slave gates may be a variety of different logic functions. The logic threshold voltage of the slave gates is substantially the same as a voltage applied to the control input of the master gate.
摘要翻译： 具有主门或逻辑门的逻辑门装置，用于响应于主器件控制从门的逻辑阈值电压。 主门和从门均具有与逻辑功能电路组合设置的两个相反的导电型晶体管。 晶体管具有与控制输入的公共栅极连接。 改变控制输入端的电压会改变门极的逻辑门限电压。 主控门中的逻辑功能通常是一个反相器，其输入和输出连接在一起并驱动从门的控制输入。 从门的逻辑功能可能是各种不同的逻辑功能。 从门的逻辑门限电压基本上与施加到主门控制输入端的电压相同。
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公开(公告)号：US06339643B1
公开(公告)日：2002-01-15
申请号：US09239683
申请日：1999-01-29
IPC分类号： H04M900
摘要： Apparatus and process for allowing a user to selectively disable all or a portion of the manual controls, e.g., the keypad and/or other buttons (including switches, keys, on-hook button, and/or other buttons) of customer premises equipment. The customer premises equipment includes a button disabling module which allows subsequent control signals relating to the particular keys or buttons which have been disabled to be essentially ignored. Thus, for instance, if an on-hook button is inadvertently depressed while the on-hook button has been disabled by the button disabling module, the telephone line interface of the telephone will not signal the termination of the telephone call to the central office. The manual controls of the customer premises equipment can be disabled by the user in any of a number of different ways. For instance, a dedicated button at either the base unit or the handset of a telephone may be provided, or a sequence or simultaneous combination of alphanumeric keys and/or other buttons may be sensed. The disabled button(s) can be re-enabled either manually by the user, or automatically, e.g., after hanging up the telephone. A timer can be included to automatically re-enable any disabled manual controls (i.e., buttons) if the user failed to manually re-enable disabled buttons before terminating the previous telephone call.
摘要翻译： 用于允许用户选择性地禁用用户驻地设备的手动控制（例如键盘和/或其他按钮（包括开关，键，挂机按钮和/或其他按钮）的全部或一部分的装置和过程。 客户驻地设备包括按钮禁用模块，其允许与被禁用的特定键或按钮相关的后续控制信号基本上被忽略。 因此，例如，如果在由按钮禁用模块禁用了挂机按钮的情况下无意中按下了挂机按钮，则电话的电话线路接口将不会向中心局通知电话呼叫的终止。 客户驻地设备的手动控制可以由用户以多种不同的方式来禁用。 例如，可以提供电话的基本单元或手机上的专用按钮，或者可以感测字母数字键和/或其他按钮的序列或同时组合。 禁用的按钮可以由用户手动重新启用，或者例如在挂断电话之后自动地重新启用。 如果用户在终止先前的电话呼叫之前无法手动重新启用禁用按钮，则可以包括定时器来自动重新启用任何禁用的手动控制（即按钮）。
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公开(公告)号：US5862187A
公开(公告)日：1999-01-19
申请号：US509563
申请日：1995-07-31
申请人： Mirmira Ramarao Dwarakanath , Kadaba R. Lakshmikumar , Angelo Rocco Mastrocola , Krishnaswamy Nagaraj , Douglas Edward Sherry
发明人： Mirmira Ramarao Dwarakanath , Kadaba R. Lakshmikumar , Angelo Rocco Mastrocola , Krishnaswamy Nagaraj , Douglas Edward Sherry
IPC分类号： H04L27/22 , H04L27/233
CPC分类号： H04L27/2338
摘要： A receiver for decoding passband signal pulses transmitted in accordance with a M-ARY phase shift keying modulation scheme, comprises a multiphase sampler for sampling received passband signal pulses in the passband frequency range so as to generate a plurality of digital words corresponding to the sampled passband signal pulses, such that each digital word represents the phase of each sampled passband signal pulse. A phase reference register or other storage device is coupled to the multiphase sampler for storing one of the digital words as a phase reference such that other digital words generated by the multiphase sampler are compared with the digital word corresponding to the phase reference for decoding the passband signal pulses.
摘要翻译： 用于解码根据M-ARY相移键控调制方案发送的通带信号脉冲的接收机包括用于在通带频率范围中对接收的通带信号脉冲进行采样的多相采样器，以产生对应于采样通带的多个数字字 信号脉冲，使得每个数字字表示每个采样的通带信号脉冲的相位。 相位参考寄存器或其他存储装置耦合到多相采样器，用于将数字字中的一个存储为相位参考，使得由多相采样器产生的其他数字字与对应于相位参考的数字字进行比较，以解码通带 信号脉冲。
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公开(公告)号：US5920203A
公开(公告)日：1999-07-06
申请号：US773453
申请日：1996-12-24
IPC分类号： H03K19/017 , H03K19/0185
CPC分类号： H03K19/01721 , H03K19/018528
摘要： An improved complementary logic driven level shifter which typically improves switching speed over the prior art diode-type circuit, and allows for symmetrical delays for both high-to-low and low-to-high transitions, thus reducing settling times. The complementary CMOS and not-CMOS inputs to the level shifter are applied to the gates of a pair of P-channel FETs and also to the gates of a pair of N-channel FETs. The sources of the P-channel FETs are coupled to a current source. The drain of each P-channel FET is coupled to the drain of the N-channel FET to which its gate is coupled, and also to the anode of a diode. The cathodes of the two diodes, and the sources of the N-channel FETs are coupled together to the anode of a grounded cathode diode. The output SELECT is the common connection point of the drains of the FETs whose gates are coupled to not-CMOS, and the complementary not-SELECT output is the drains of the FETs whose gates are coupled to CMOS. In a second embodiment, the two diodes across the N-channel FETs are replaced by a diode from the current source to the anode of the grounded-cathode diode.
摘要翻译： 一种改进的互补逻辑驱动电平移位器，其通常提高了现有技术的二极管型电路的开关速度，并且允许从高到低和从低到高的转换的对称延迟，从而减少稳定时间。 电平移位器的互补CMOS和非CMOS输入端被施加到一对P沟道FET的栅极，也被施加到一对N沟道FET的栅极。 P沟道FET的源极耦合到电流源。 每个P沟道FET的漏极耦合到其栅极耦合到的N沟道FET的漏极，并且耦合到二极管的阳极。 两个二极管的阴极和N沟道FET的源极耦合到接地阴极二极管的阳极。 输出SELECT是其栅极耦合到非CMOS的FET的漏极的公共连接点，互补的非选择输出是其栅极耦合到CMOS的FET的漏极。 在第二实施例中，跨越N沟道FET的两个二极管被二极管从电流源替代为接地阴极二极管的阳极。
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6.发明授权Apparatus for detecting clock failure within a fixed number of cycles of the clock 有权用于在时钟的固定周期内检测时钟故障的装置公开(公告)号：US06668334B1
公开(公告)日：2003-12-23
申请号：US09604842
申请日：2000-06-27
申请人： Christopher John Abel , Angelo Rocco Mastrocola , Douglas Edward Sherry , William Burdett Wilson
发明人： Christopher John Abel , Angelo Rocco Mastrocola , Douglas Edward Sherry , William Burdett Wilson
IPC分类号： G06F104
CPC分类号： H03K5/19 , G01R31/31725 , H03K5/1515 , H04L7/0083
摘要： A loss-of-clock (LOC) detector circuit detects a clock failure substantially within a specified number of clock periods and generates a loss-of-clock signal. The LOC detector includes a frequency-to-current converter which generates a charging current substantially proportional to a frequency of an input clock. A capacitor accepts the charging current and provides a terminal voltage that changes in response to the charging current. An edge detector receives the input clock signal as an input and produces an output pulse on an edge of the input clock signal. A switch is coupled to the capacitor such that the capacitor is discharged to a reference potential when the switch is closed. The switch is controlled by the edge detector to close when the edge detector output pulse is asserted. A comparator generates a loss-of-clock signal when the voltage on the capacitor passes a trip voltage of the comparator.
摘要翻译： 时钟（LOC）检测器电路基本上在指定数量的时钟周期内检测时钟故障，并产生时钟损失信号。 LOC检测器包括频率到电流转换器，其产生基本上与输入时钟的频率成比例的充电电流。 电容器接受充电电流并提供响应于充电电流而改变的端电压。 边缘检测器接收输入时钟信号作为输入，并在输入时钟信号的边沿产生输出脉冲。 开关耦合到电容器，使得当开关闭合时，电容器被放电到参考电位。 当边缘检测器输出脉冲被置位时，开关由边沿检测器控制。 当电容器上的电压通过比较器的跳闸电压时，比较器产生时钟损失信号。
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公开(公告)号：US06356132B1
公开(公告)日：2002-03-12
申请号：US09495522
申请日：2000-01-31
IPC分类号： H03H1126
摘要： An integrated circuit has a plurality of signal paths, at least one of which has a delay cell. The delay cell has an input terminal for receiving an signal from the signal path, and a plurality of delay paths for generating a corresponding plurality of delayed signals delayed by different delays from the input signal. At least one of the delay paths employs two different-delay subpaths coupled in parallel to provide a delayed signal delayed by an interpolated delay. A multiplexer (MUX) of the delay cell provides one of the delayed signals as an output signal to the signal path based on a control input signal applied to the multiplexer.
摘要翻译： 集成电路具有多个信号路径，其中至少一个具有延迟单元。 所述延迟单元具有用于从所述信号路径接收信号的输入端子以及用于从所述输入信号产生延迟了不同延迟的相应多个延迟信号的多个延迟路径。 延迟路径中的至少一个采用并联耦合的两个不同延迟子路径，以提供延迟由内插延迟延迟的信号。 延迟单元的多路复用器（MUX）基于施加到多路复用器的控制输入信号，将一个延迟信号提供给信号路径的输出信号。
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