Method of fabricating UMOS semiconductor devices using a self-aligned,
reduced mask process
    1.
    发明授权
    Method of fabricating UMOS semiconductor devices using a self-aligned, reduced mask process 失效
    使用自对准减小掩模工艺制造UMOS半导体器件的方法

    公开(公告)号:US5940689A

    公开(公告)日:1999-08-17

    申请号:US885921

    申请日:1997-06-30

    CPC分类号: H01L29/7813

    摘要: A method of fabricating a UMOS semiconductor device includes a blanket implant of an N type dopant into a surface of a substrate (for forming source regions), a high energy implant of a P type dopant into the substrate (for forming body regions), an etch through a hard mask to form trenches and mesas (each of the mesas having a source region at its top and a body region below), and concurrently (i) providing a gate dielectric on the sidewalls of the trenches and (ii) redistributing the dopants so that the body regions extend deeper into the substrate beneath the centers of the mesas than adjacent the walls of the trenches. Contact windows are etched in the mesas to allow electrical contact with the source regions and the body regions. The initial implant of P type dopant may be a blanket implant or an implant through a mask which concentrates the P type dopant in the centers of the mesas.

    摘要翻译: 一种制造UMOS半导体器件的方法包括将N型掺杂剂覆盖到衬底的表面(用于形成源极区)中,将P型掺杂剂的高能量注入到衬底(用于形成体区)中, 通过硬掩模蚀刻以形成沟槽和台面(每个台面在其顶部具有源区域和下面的主体区域),并且同时(i)在沟槽的侧壁上提供栅极电介质,以及(ii)重新分配 掺杂剂,使得身体区域在台面的中心下方比邻近沟槽的壁更深地延伸到基底之下。 接触窗被蚀刻在台面中以允许与源区域和身体区域的电接触。 P型掺杂剂的初始注入可以是覆盖注入或通过掩模的注入,其将P型掺杂剂集中在台面的中心。