公开(公告)号：US5940689A

公开(公告)日：1999-08-17

申请号：US885921

申请日：1997-06-30

申请人： Christopher L. Rexer ,  Mark L. Rineheimer ,  John M. S. Neilson ,  Thomas E. Grebs

发明人： Christopher L. Rexer ,  Mark L. Rineheimer ,  John M. S. Neilson ,  Thomas E. Grebs

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/332 ,  H01L21/00

CPC分类号： H01L29/7813

摘要： A method of fabricating a UMOS semiconductor device includes a blanket implant of an N type dopant into a surface of a substrate (for forming source regions), a high energy implant of a P type dopant into the substrate (for forming body regions), an etch through a hard mask to form trenches and mesas (each of the mesas having a source region at its top and a body region below), and concurrently (i) providing a gate dielectric on the sidewalls of the trenches and (ii) redistributing the dopants so that the body regions extend deeper into the substrate beneath the centers of the mesas than adjacent the walls of the trenches. Contact windows are etched in the mesas to allow electrical contact with the source regions and the body regions. The initial implant of P type dopant may be a blanket implant or an implant through a mask which concentrates the P type dopant in the centers of the mesas.

摘要翻译： 一种制造UMOS半导体器件的方法包括将N型掺杂剂覆盖到衬底的表面（用于形成源极区）中，将P型掺杂剂的高能量注入到衬底（用于形成体区）中， 通过硬掩模蚀刻以形成沟槽和台面（每个台面在其顶部具有源区域和下面的主体区域），并且同时（i）在沟槽的侧壁上提供栅极电介质，以及（ii）重新分配 掺杂剂，使得身体区域在台面的中心下方比邻近沟槽的壁更深地延伸到基底之下。 接触窗被蚀刻在台面中以允许与源区域和身体区域的电接触。 P型掺杂剂的初始注入可以是覆盖注入或通过掩模的注入，其将P型掺杂剂集中在台面的中心。

公开(公告)号：US5422288A

公开(公告)日：1995-06-06

申请号：US246307

申请日：1994-05-19

申请人： John M. S. Neilson ,  Christopher L. Rexer ,  Carl F. Wheatley, Jr.

发明人： John M. S. Neilson ,  Christopher L. Rexer ,  Carl F. Wheatley, Jr.

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66712 ,  H01L21/8234 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/0847

摘要： A MOS-gated semiconductor device may be manufactured by a process in which the neck region of the device is doped through a previously deposited polysilicon gate. In the method of the present invention, the dopant in the neck region of the device is not subjected to the same temperature history as the body dopant, thereby providing means to increase the ruggedness of the device and providing means by which the threshold voltage of the device may be controlled.

摘要翻译： MOS门控半导体器件可以通过其中器件的颈区通过先前沉积的多晶硅栅极掺杂的工艺来制造。 在本发明的方法中，器件的颈部区域中的掺杂剂不会受到与体掺杂物相同的温度历史的影响，从而提供了增加器件耐用性的手段，并提供了将器件的阈值电压 设备可以被控制。

公开(公告)号：US5323036A

公开(公告)日：1994-06-21

申请号：US822732

申请日：1992-01-21

申请人： John M. S. Neilson ,  Frederick P. Jones ,  Joseph A. Yedinak ,  Christopher L. Rexer

发明人： John M. S. Neilson ,  Frederick P. Jones ,  Joseph A. Yedinak ,  Christopher L. Rexer

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L27/10 ,  H01L29/78

CPC分类号： H01L29/0696 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/4238

摘要： In a power FET composed of a substrate having upper and lower surfaces, the FET providing a current flow path between the upper and lower surfaces, and the FET having a plurality of drain regions extending to the substrate upper surface and an insulated gate electrode disposed on the upper surface, the improvement wherein said drain regions are disposed in a hexagonal lattice pattern, and said gate electrode comprises: a plurality of gate segments each covering a respective drain region; and a plurality of connecting segments each connecting together three of said gate segments.

摘要翻译： 在由具有上表面和下表面的衬底构成的功率FET中，FET在上表面和下表面之间提供电流流动路径，并且具有延伸到衬底上表面的多个漏区的FET和设置在衬底上的绝缘栅电极 上表面，其中所述漏极区域以六边形格子图案设置，并且所述栅极电极包括：多个栅极段，每个栅极段覆盖相应的漏极区域; 以及多个连接段，每个连接段将三个所述栅极段连接在一起。

公开(公告)号：US5455442A

公开(公告)日：1995-10-03

申请号：US375714

申请日：1995-01-20

申请人： John M. S. Neilson ,  Wolfgang F. W. Dietz

发明人： John M. S. Neilson ,  Wolfgang F. W. Dietz

IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L29/68

CPC分类号： H01L29/7398 ,  H01L24/05 ,  H01L29/7395 ,  H01L29/7809 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/1305 ,  H01L2924/13091

摘要： The performance of COMFET-based electrical switches may be improved by connecting a MOSFET substantially in parallel with the COMFET. In a monolithic embodiment, a MOSFET drain region may be added to a surface of a COMFET and shorted to the emitter region of the COMFET. The invention decreases the turn-off time of the COMFET, reduces the discontinuity at current direction reversal and increases the latch-up current of a semiconductor switch.

摘要翻译： 通过连接基本上与COMFET并联的MOSFET，可以提高基于COMFET的电气开关的性能。 在单片实施例中，可以将MOSFET漏极区域添加到COMFET的表面并短路到COMFET的发射极区域。 本发明降低了COMFET的关断时间，减小了电流方向反转的不连续性，并增加了半导体开关的闭锁电流。

公开(公告)号：US4639754A

公开(公告)日：1987-01-27

申请号：US705371

申请日：1985-02-25

申请人： Carl F. Wheatley, Jr. ,  John M. S. Neilson ,  John P. Russell

发明人： Carl F. Wheatley, Jr. ,  John M. S. Neilson ,  John P. Russell

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/1095

摘要： An IGFET device includes a semiconductor wafer having a first conductivity type drain region contiguous with a wafer surface. A second conductivity type body region extends into the wafer from the wafer surface so as to form a body/drain PN junction having an intercept at the surface; the body region further including a body-contact portion of relatively high conductivity disposed at the surface. A first conductivity type source region extends into the wafer so as to form a source/body PN junction which has first and second intercepts at the surface. The first intercept is spaced from the body/drain intercept so as to define a channel region in the body region at the surface, and the second intercept is contiguous with the body contact portion. The second intercept is relatively narrowly spaced from the first intercept along most of the length of the first intercept and is relatively widely spaced from the first intercept at one or more predetermined portions. A source electrode contacts the body-contact portion and the source region on the wafer surface.

摘要翻译： IGFET器件包括具有与晶片表面相邻的第一导电型漏极区域的半导体晶片。 第二导电类型体区域从晶片表面延伸到晶片中，以形成在表面具有截距的主体/漏极PN结; 所述主体区域还包括设置在所述表面处的相对高导电性的身体接触部分。 第一导电类型源极区域延伸到晶片中，以形成在表面具有第一和第二截距的源极/主体PN结。 第一截距与身体/排水截距间隔开，以便在表面的身体区域中限定通道区域，并且第二截距与身体接触部分相邻。 第二截距与第一截距的大部分长度上的第一截距相对较窄地间隔开，并且与一个或多个预定部分处的第一截距相比较宽。 源电极接触晶片表面上的体接触部分和源极区域。

公开(公告)号：US4631564A

公开(公告)日：1986-12-23

申请号：US664027

申请日：1984-10-23

申请人： John M. S. Neilson ,  Carl F. Wheatley, Jr. ,  Norbert W. Brackelmanns

发明人： John M. S. Neilson ,  Carl F. Wheatley, Jr. ,  Norbert W. Brackelmanns

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7395

摘要： A VDMOS device comprises a semiconductor wafer having a major surface with a first conductivity type drain region thereat. An array of second conductivity type body regions, spaced from each other by distance D, is diffused into the drain region from the first surface. The body regions each include a relatively high conductivity supplementary body region and a first conductivity type source region diffused therein from within the first surface boundary thereof. The spacing between each source region and the drain region defines a channel region at the first surface. A source electrode contacts the source and body regions and an insulated gate electrode overlies each channel region. A gate bond pad, in direct contact with the gate electrode, overlies a second conductivity type gate shield region and is insulated therefrom. The gate shield region is contiguous with the drain region and is spaced from the neighboring channel regions by distance D. The gate shield region includes a plurality of contact areas proximate to the periphery thereof and a plurality of relatively low conductivity portions disposed between the contact areas and the drain region. The source electrode ohmically contacts these contact areas.

摘要翻译： VDMOS器件包括半导体晶片，其主表面具有第一导电型漏极区域。 通过距离D彼此间隔开的第二导电类型体区域的阵列从第一表面扩散到漏极区域。 主体区域各自包括相对高的导电性补充体区域和从其第一表面边界内扩散的第一导电型源区域。 每个源极区域和漏极区域之间的间隔限定在第一表面处的沟道区域。 源电极接触源极和主体区域，绝缘栅电极覆盖每个沟道区域。 与栅电极直接接触的栅极接合焊盘覆盖在第二导电类型的栅极屏蔽区域上并与之绝缘。 栅极屏蔽区域与漏极区域相邻并且与相邻沟道区域间隔开距离D.栅极屏蔽区域包括靠近其周边的多个接触区域和设置在接触区域之间的多个相对较低的导电部分 和漏极区域。 源电极欧姆接触这些接触区域。

公开(公告)号：US5095343A

公开(公告)日：1992-03-10

申请号：US609054

申请日：1990-11-06

申请人： Stanley J. Klodzinski ,  Harold R. Ronan, Jr. ,  John M. S. Neilson ,  Carl F. Wheatley, Jr.

发明人： Stanley J. Klodzinski ,  Harold R. Ronan, Jr. ,  John M. S. Neilson ,  Carl F. Wheatley, Jr.

IPC分类号： H01L29/06 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/7395

摘要： A VDMOS device includes a wafer of semiconductor material having first and second opposed major surfaces. A drain region of a first conductivity type extends along the one major surface. A plurality of body regions of a second conductivity type is in the body region at the one major surface. Each body region forms with the drain region a body/drain PN junction, the intersection of which with the first major surface is in a closed path, preferably a hexagon. A plurality of spaced source regions of the one conductivity type are in each of the body regions with each source region being positioned opposite the space between two source regions in the adjacent body region. Each source region forms with the body region a source/body PN junction. A portion of each of the source/body PN junctions is adjacent to but spaced from its respective drain/body PN junction to form a channel region therebetween. An insulated gate is over the first major surface and the channel regions. The plurality of spaced channel regions in each of the body regions provides the device with improved surface operating area.

摘要翻译： VDMOS器件包括具有第一和第二相对主表面的半导体材料晶片。 第一导电类型的漏极区沿着一个主表面延伸。 第二导电类型的多个体区在一个主表面处于体区。 每个体区与漏区形成体/漏PN结，其与第一主表面的交点处于闭合路径，优选为六边形。 一个导电类型的多个间隔的源极区域在每个体区域中，每个源极区域与相邻体区域中的两个源极区域之间的空间相对。 每个源区域与体区域形成源/体PN结。 源极/主体PN结中的每一个的一部分与其相应的漏极/主体PN结相邻但间隔开，以在它们之间形成沟道区。 绝缘栅极位于第一主表面和沟道区之上。 每个身体区域中的多个间隔通道区域为装置提供了改进的表面操作面积。

公开(公告)号：US4398206A

公开(公告)日：1983-08-09

申请号：US233488

申请日：1981-02-11

申请人： John M. S. Neilson

发明人： John M. S. Neilson

IPC分类号： H01L27/07 ,  H01L27/02

CPC分类号： H01L27/0755

摘要： A semiconductor device including a transistor, diode and resistor comprises a body of semiconductor material formed with conventional emitter, base and collector regions. The collector region forms one electrode of the diode with the other electrode being formed in the region forming the base of the transistor and being separated from the base by an isolation ring. The contact between the emitter and the other electrode are integral, but are insulated from the isolation ring.

摘要翻译： 包括晶体管，二极管和电阻器的半导体器件包括由常规发射极，基极和集电极区域形成的半导体材料体。 集电极区域形成二极管的一个电极，另一个电极形成在形成晶体管的基极的区域中，并通过隔离环与基极分离。 发射极和另一个电极之间的接触是一体的，但与隔离环绝缘。

公开(公告)号：US4297149A

公开(公告)日：1981-10-27

申请号：US146380

申请日：1980-05-05

申请人： Patrick R. Koons ,  John M. S. Neilson

发明人： Patrick R. Koons ,  John M. S. Neilson

IPC分类号： H01L21/314 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/265 ,  G06F15/46 ,  H01L21/205

CPC分类号： H01L21/324 ,  H01L21/3105 ,  Y10S257/905 ,  Y10S438/958

摘要： The breakdown voltage of high voltage semiconductor devices passivated with SiPOS deteriorates if the devices are allowed to soak at temperatures in the 400.degree. C. to 525.degree. C. range. The original breakdown voltage is recovered by annealing the devices at a temperature of above about 550.degree. C. prior to metallization and alloying the metal at less than 425.degree. C.

摘要翻译： 如果允许器件在400℃至525℃的温度范围内浸泡，则SiPOS钝化的高电压半导体器件的击穿电压会降低。 在金属化之前，在高于约550℃的温度下对器件进行退火并使金属在小于425℃下合金化来回收初始击穿电压。

公开(公告)号：US5243211A

公开(公告)日：1993-09-07

申请号：US797054

申请日：1991-11-25

申请人： John M. S. Neilson

发明人： John M. S. Neilson

IPC分类号： H01L23/58 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7395 ,  H01L23/585 ,  H01L29/7802 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/42368 ,  H01L2924/0002

摘要： In a power FET composed of a substrate having upper and lower surfaces and having a semiconductor body providing a current flow path between the upper and lower surfaces and having at least one body region of a first conductivity type which extends to said upper surface; and at least one base region extending into the substrate from the upper surface, the base region being of a second conductivity type opposite to the first conductivity type, the base region being at least partially disposed in the current flow path and having at least two portions between which the at least one body region extends, and the FET further having an insulated gate disposed at the upper surface above the body region, the substrate further has a shielding region of the second conductivity type extending into the at least one body region from the upper surface, at a location below the gate electrode and enclosed by the base region portions, and spaced from the base region by parts of the body region of the first conductivity type. A second shielding region of the second conductivity type extends into the body region from the upper surface and extends along the peripheral edge of the substrate.

摘要翻译： 在由具有上表面和下表面的衬底组成的功率FET中，并具有半导体本体，该半导体本体在上表面和下表面之间提供电流流动通道，并具有延伸到所述上表面的至少一个第一导电类型的体区; 以及从上表面延伸到基板中的至少一个基区，所述基区具有与第一导电类型相反的第二导电类型，所述基区至少部分地设置在电流流动路径中，并且具有至少两部分 其中所述至少一个体区域延伸，并且所述FET还具有设置在所述身体区域上方的上表面处的绝缘栅极，所述衬底还具有从所述第二导电类型的屏蔽区域延伸到所述至少一个体区域中的屏蔽区域， 上表面，位于栅极电极下方并由基极区域部分包围，并且与第一导电类型的主体区域的一部分与基极区隔开。 第二导电类型的第二屏蔽区域从上表面延伸到主体区域中并且沿着基板的周边边缘延伸。