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公开(公告)号：US07458043B1
公开(公告)日：2008-11-25
申请号：US11227548
申请日：2005-09-15
CPC分类号： G06F17/5022 , G01R31/318357 , G06F11/261 , G06F11/263
摘要： Various approaches for generating input data for simulating a circuit design are disclosed. In one approach, a test generator program is generated from a main program that uses a test generator class library. The test generator class library includes a software driver class corresponding to the hardware driver, and the software driver class includes a storage class corresponding to each memory within the hardware driver, a first set including at least one method for writing function codes to a first object of the storage class, and a second set including at least one method for writing data to a second object of the storage class. Function codes are written to the first object of the storage class in response to a call by the test generator program to a method in the first set. Data of a first type is written to the second object of the storage class in response to a call by the test generator program to a method in the second set, wherein the data of the first type is data to be provided by the driver as input to the simulated circuit design.
摘要翻译： 公开了用于生成用于模拟电路设计的输入数据的各种方法。 在一种方法中，从使用测试生成器类库的主程序生成测试生成器程序。 所述测试生成器类库包括与所述硬件驱动程序相对应的软件驱动器类，并且所述软件驱动器类包括与所述硬件驱动器内的每个存储器相对应的存储类，第一组包括至少一种将功能代码写入到第一对象的方法 以及包括至少一种用于将数据写入到存储类的第二对象的方法的第二集合。 响应于测试发生器程序对第一组中的方法的调用，函数代码被写入存储类的第一对象。 响应于测试发生器程序对第二组中的方法的调用，将第一类型的数据写入存储类的第二对象，其中第一类型的数据是由驱动程序作为输入提供的数据 到模拟电路设计。
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2.发明授权Method and apparatus for creating integrated circuit simulator test source files 失效用于创建集成电路模拟器测试源文件的方法和装置公开(公告)号：US07386434B1
公开(公告)日：2008-06-10
申请号：US10783816
申请日：2004-02-20
IPC分类号： G06F17/50
CPC分类号： G01R31/318357
摘要： An apparatus and method for generating test files for design verification of a simulated integrated circuit design such as a cache memory circuit, that involve steps of creating a series of functions, updating a data integrity buffer after each function is created, creating a series of integrity check functions from the data in the data integrity buffer, and writing the series of functions and the series of integrity check functions to a test file. This file can be compiled if necessary and executed by a software or hardware simulator.
摘要翻译： 一种用于生成诸如高速缓冲存储器电路的模拟集成电路设计的设计验证的测试文件的装置和方法，其包括创建一系列功能的步骤，在创建每个功能之后更新数据完整性缓冲器，创建一系列完整性 从数据完整性缓冲区中的数据检查功能，并将一系列功能和一系列完整性检查功能写入测试文件。 如果需要，可以编译该文件，并由软件或硬件模拟器执行。
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3.发明授权公开(公告)号：US07222064B1
公开(公告)日：2007-05-22
申请号：US10683029
申请日：2003-10-10
CPC分类号： G06F9/45537
摘要： Techniques are described for emulating inter-processor communications between multiple instruction processors. The techniques provide inter-processor message accounting and error detection. A system, for example, includes software executing within an emulation environment provided by a computing system. The emulation software emulates an instruction processor having an interface to receive inter-processor messages. During emulation the emulated instruction processor calculates an actual count of the inter-processor messages received during emulation. A compiler executing on the computing system compiles test software to output an instruction stream for execution by the emulated instruction processor. The compiler calculates an expected count of inter-processor messages that the emulated instruction processor is expected to receive during emulation. Emulation control software executing on the computing system generates a report that presents the expected count of the inter-processor messages and the actual count of the inter-processor messages.
摘要翻译： 描述了用于模拟多个指令处理器之间的处理器间通信的技术。 这些技术提供了处理器间消息计费和错误检测。 例如，系统包括在由计算系统提供的仿真环境中执行的软件。 仿真软件模拟具有接收处理器间消息的接口的指令处理器。 在仿真期间，仿真指令处理器计算在仿真期间接收的处理器间信息的实际计数。 在计算系统上执行的编译器编译测试软件以输出用于由仿真指令处理器执行的指令流。 编译器计算仿真指令处理器期望在仿真期间接收的处理器间消息的期望计数。 在计算系统上执行的仿真控制软件产生呈现处理器间消息的期望计数和处理器间消息的实际计数的报告。
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