公开(公告)号：US07222064B1

公开(公告)日：2007-05-22

申请号：US10683029

申请日：2003-10-10

申请人： Jason D. Sollom ,  James A. Williams ,  Christopher M. Cischke

发明人： Jason D. Sollom ,  James A. Williams ,  Christopher M. Cischke

IPC分类号： G06F9/455 ,  G06F9/00

CPC分类号： G06F9/45537

摘要： Techniques are described for emulating inter-processor communications between multiple instruction processors. The techniques provide inter-processor message accounting and error detection. A system, for example, includes software executing within an emulation environment provided by a computing system. The emulation software emulates an instruction processor having an interface to receive inter-processor messages. During emulation the emulated instruction processor calculates an actual count of the inter-processor messages received during emulation. A compiler executing on the computing system compiles test software to output an instruction stream for execution by the emulated instruction processor. The compiler calculates an expected count of inter-processor messages that the emulated instruction processor is expected to receive during emulation. Emulation control software executing on the computing system generates a report that presents the expected count of the inter-processor messages and the actual count of the inter-processor messages.

摘要翻译： 描述了用于模拟多个指令处理器之间的处理器间通信的技术。 这些技术提供了处理器间消息计费和错误检测。 例如，系统包括在由计算系统提供的仿真环境中执行的软件。 仿真软件模拟具有接收处理器间消息的接口的指令处理器。 在仿真期间，仿真指令处理器计算在仿真期间接收的处理器间信息的实际计数。 在计算系统上执行的编译器编译测试软件以输出用于由仿真指令处理器执行的指令流。 编译器计算仿真指令处理器期望在仿真期间接收的处理器间消息的期望计数。 在计算系统上执行的仿真控制软件产生呈现处理器间消息的期望计数和处理器间消息的实际计数的报告。

公开(公告)号：US07228266B1

公开(公告)日：2007-06-05

申请号：US10729666

申请日：2003-12-05

申请人： Jason D. Sollom ,  James A. Williams

发明人： Jason D. Sollom ,  James A. Williams

IPC分类号： G06F9/455

CPC分类号： G06F9/45504 ,  G06F9/45537 ,  G06F11/3652 ,  G06F11/366 ,  G06F11/3664

摘要： Techniques are described for emulating an instruction processor for use during the development of a computer system. Specifically, the techniques describe an emulated instruction processor that accurately and efficiently emulates an instruction processor having separate interfaces to fetch op-codes and operands. Further, the emulated instruction processor may provide detection of errors associated with the separate interfaces. By making use of the techniques described herein, detailed information relating to errors associated with the memory architecture may be gathered for use in verifying components within the memory architecture, such as first and second-level caches.

摘要翻译： 描述了用于仿真在计算机系统开发期间使用的指令处理器的技术。 具体地说，这些技术描述了一种仿真指令处理器，其精确而有效地仿真具有单独接口的指令处理器来获取操作码和操作数。 此外，仿真指令处理器可提供与单独接口相关联的错误的检测。 通过利用本文描述的技术，可以收集与存储器架构相关联的错误的详细信息，以用于验证存储器架构内的组件，例如第一级和第二级高速缓存。

公开(公告)号：US07096322B1

公开(公告)日：2006-08-22

申请号：US10683028

申请日：2003-10-10

申请人： Jason D. Sollom ,  James A. Williams

发明人： Jason D. Sollom ,  James A. Williams

IPC分类号： G06F12/02

CPC分类号： G06F9/30076 ,  G06F8/4442 ,  G06F9/30047 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/455

摘要： Techniques are described for accurately and efficiently emulating an instruction processor having a write buffer. The described techniques may be utilized to quickly develop an emulated instruction processor that provides a fully-functional write buffer interface in an efficient and elegant manner. For example, a system is described that includes a computing system that provides an emulation environment, and software executing within the emulation environment that emulates an instruction processor having a write buffer interface and a memory interface. The software emulates the instruction processor by selectively outputting a write request on the write buffer interface or the memory interface in response to an emulation control instruction embedded within an instruction stream.

摘要翻译： 描述了用于准确和有效地仿真具有写入缓冲器的指令处理器的技术。 所描述的技术可以用于快速开发以有效和优雅的方式提供全功能写入缓冲器接口的仿真指令处理器。 例如，描述了一种系统，其包括提供仿真环境的计算系统和在仿真环境中执行的软件，其仿真具有写缓冲器接口和存储器接口的指令处理器。 该软件通过在写入缓冲器接口或存储器接口上选择性地输出写入请求来仿真指令处理器，以响应嵌入指令流中的仿真控制指令。