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公开(公告)号：US07254716B1
公开(公告)日：2007-08-07
申请号：US10324976
申请日：2002-12-20
CPC分类号： G06F21/74 , G06F21/6218 , G06F21/72 , G06F2221/2105
摘要： A circuit generally comprising a plurality of master modules and a supervisor module is disclosed. The supervisor module may be configured to (i) detect a target address and a particular master module of the master modules initiating a transaction on a bus, (ii) identify a predetermined authorization in response to the particular master module, the target address and a current security mode of at least three security modes and (iii) subvert the transaction in response to the predetermined authorization restricting the transaction.
摘要翻译： 公开了通常包括多个主模块和主管模块的电路。 主管模块可以被配置为（i）检测在总线上发起事务的主模块的目标地址和特定主模块，（ii）响应于特定主模块，目标地址和目标地址识别预定授权 至少三种安全模式的当前安全模式，以及（iii）响应于限制该交易的预定授权来颠覆交易。
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2.发明授权公开(公告)号：US07254720B1
公开(公告)日：2007-08-07
申请号：US10326440
申请日：2002-12-20
CPC分类号： G06F12/1491 , G06F21/554 , G06F21/572 , G06F21/71 , G06F21/74
摘要： A circuit generally comprising a first memory, a processor and a logic block is disclosed. The first memory may store (i) a write instruction to store a non-highest security value of at least three security values in a register and (ii) a jump instruction to a second memory. The processor may have a pipeline and may be configured to (i) bootstrap to the first memory while the register stores a highest security value of the security values and (ii) execute the jump instruction following the write instruction. The logic block may be configured to (i) detect the write instruction in an execution stage of the pipeline and (ii) store the non-highest security value in the register in response to detecting the write instruction in a write back stage of the pipeline.
摘要翻译： 公开了通常包括第一存储器，处理器和逻辑块的电路。 第一存储器可以存储（i）用于在寄存器中存储至少三个安全值的非最高安全值的写指令，以及（ii）到第二存储器的跳转指令。 处理器可以具有流水线并且可以被配置为（i）引导到第一存储器，而寄存器存储安全值的最高安全性值，以及（ii）执行写指令之后的跳转指令。 逻辑块可以被配置为（i）在流水线的执行阶段中检测写指令，并且响应于在流水线的回写阶段检测写指令，将非最高安全值存储在寄存器中 。
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公开(公告)号：US07228440B1
公开(公告)日：2007-06-05
申请号：US10325382
申请日：2002-12-20
CPC分类号： G01R31/318555 , G01R31/31719 , G01R31/318591
摘要： A circuit generally comprising a logic module and a security module is disclosed. The logic module may be configured to set a plurality of values to a plurality of predetermined values respectively while in a scan mode. The security module may be configured to (i) disable a scan capability of the values while in a non-lowest security mode of at least three security modes and (ii) enabling the scan capability while in a lowest security mode of the security modes.
摘要翻译： 通常包括逻辑模块和安全模块的电路被公开。 逻辑模块可以被配置为在扫描模式下分别将多个值设置为多个预定值。 安全模块可以被配置为（i）在处于至少三种安全模式的非最低安全模式的同时禁用该值的扫描能力，以及（ii）在安全模式的最低安全模式下启用扫描能力。
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公开(公告)号：US07117352B1
公开(公告)日：2006-10-03
申请号：US10325192
申请日：2002-12-20
IPC分类号： G06F9/445
CPC分类号： G01R31/31719 , G01R31/31705 , G01R31/318533
摘要： A circuit generally comprising a debug port and a processor is disclosed. The processor may be configured to (i) bootstrap to a first memory, (ii) disable said debug port while in a first mode of at least three modes, (iii) authenticate said debug port while in a second mode of said modes and (iv) disable said debug port in response to failing said authentication.
摘要翻译： 通常包括调试端口和处理器的电路被公开。 处理器可以被配置为（i）引导到第一存储器，（ii）在处于至少三种模式的第一模式时禁用所述调试端口，（iii）在所述模式的第二模式中验证所述调试端口，并且 iv）响应于所述认证失败而禁用所述调试端口。
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公开(公告)号：US06968420B1
公开(公告)日：2005-11-22
申请号：US10325132
申请日：2002-12-20
IPC分类号： G01R31/317 , G01R31/3185 , G06F12/00 , H04N5/00
CPC分类号： G01R31/31719 , G01R31/318533 , H04N21/4405 , H04N21/4623
摘要： A circuit generally comprising a first memory, a second memory and a processor is disclosed. The first memory may store an instruction to read an updated security value of at least three security values. The second memory may store (i) the updated security value and (ii) information related to security of the circuit. The processor may be configured to (i) execute the instruction while a register stores a highest security value of the security values, (ii) copy the information from the second memory to a third memory in response to the update security value being greater than a current security value of the security values stored in the third memory and (iii) ignore the information in the second memory in response to the updated security value being no greater than the current security value.
摘要翻译： 公开了通常包括第一存储器，第二存储器和处理器的电路。 第一存储器可以存储读取至少三个安全值的更新的安全值的指令。 第二存储器可以存储（i）更新的安全值和（ii）与电路的安全性有关的信息。 处理器可以被配置为（i）在寄存器存储安全值的最高安全性值的同时执行指令，（ii）响应于更新安全性值大于第一存储器的信息将信息从第二存储器复制到第三存储器 存储在第三存储器中的安全值的当前安全值，以及（iii）响应于更新的安全值不大于当前安全值，忽略第二存储器中的信息。
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公开(公告)号：US06408076B1
公开(公告)日：2002-06-18
申请号：US09034656
申请日：1998-03-03
申请人： Simon Bewick
发明人： Simon Bewick
IPC分类号： H04N7167
CPC分类号： H04N21/4405 , H04N7/1675 , H04N21/4623
摘要： In order to descramble sections of scrambled data interleaved with sections of unscrambled data in a transport stream of broadcast video data, while leaving the sections with the original timing relationship in the transport stream, a common data flow path (1-5) is provided both for sections of scrambled data and sections of unscrambled data and signal path loops (6,7; 8,9) including cipher means (62,64) to enable the descrambling of scrambled data, and a control state machine for controlling the flow of data through said common data flow path and said signal path loops to enable passage of unscrambled data sections and descrambling of scrambled data sections, while maintaining the desired relative positions of the data sections.
摘要翻译： 为了在广播视频数据的传输流中解扰与未加扰数据的部分交织的加扰数据的部分，同时在传输流中留下具有原始定时关系的部分，提供公共数据流路径（1-5） 对于加扰数据的部分和包括加密装置（62,64）的未加扰数据和信号路径环路（6,7,8,9）的部分，以使能加密数据的解扰，以及用于控制数据流的控制状态机 通过所述公共数据流路径和所述信号路径环路以使得能够通过未加扰的数据部分和对加扰数据部分进行解扰，同时保持数据部分的所需相对位置。
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公开(公告)号：US6072873A
公开(公告)日：2000-06-06
申请号：US34657
申请日：1998-03-03
申请人： Simon Bewick
发明人： Simon Bewick
IPC分类号： H04N7/167
CPC分类号： H04N7/1675 , H04N21/2389 , H04N21/43853
摘要： In order to implement the Digital Video Broadcasting descrambling algorithm in the context of MPEG compressed data streams containing interleaved sections of scrambled and unscrambled data, at a data rate of 60 MBits/sec with a clock of 2.7 MHz, a stream cipher has an input to receive scrambled video data, and an output coupled to a block cipher for providing descrambled data, the stream cipher comprises shift register means for holding input data coupled to a first mapping logic mechanism comprising at least a first logic means and a second logic means coupled in sequence and arranged to carry out similar logical steps, and the block cipher means comprising shift register means for holding the output of the stream cipher means and a second logic mapping mechanism, comprising at least a first logic means, a second logic means, a third logic means and a fourth logic means coupled in sequence being arranged to carry out similar logical steps.
摘要翻译： 为了在包含加密和未加扰数据的交织部分的MPEG压缩数据流的上下文中实现数字视频广播解扰算法，以具有2.7MHz的时钟的数据速率为60MBits /秒，流密码具有输入到 接收加扰的视频数据，以及耦合到块密码以输出解扰数据的输出，流密码包括移位寄存器装置，用于保存耦合到第一映射逻辑机制的输入数据，该第一映射逻辑机构至少包括第一逻辑装置和耦合在第二逻辑装置中的第二逻辑装置 并且被布置为执行类似的逻辑步骤，并且块密码装置包括用于保持流密码装置的输出的移位寄存器装置和第二逻辑映射机制，其包括至少第一逻辑装置，第二逻辑装置，第三逻辑装置 逻辑装置和顺序耦合的第四逻辑装置被布置成执行类似的逻辑步骤。
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