公开(公告)号：US20120236852A1

公开(公告)日：2012-09-20

申请号：US13232717

申请日：2011-09-14

Applicant: Chu-Ming Lin ,  Chih-Peng Chang

Inventor： Chu-Ming Lin ,  Chih-Peng Chang

IPC: H04L12/56

CPC classification number: H04L49/351

Abstract: The invention provides an electronic apparatus. In one embodiment, the electronic apparatus comprises a plurality of ports, an Ethernet circuit, a port switch, and a flow control scheduler. The Ethernet circuit generates a plurality of transmitted packets according to transmitted data sent from the host, and derives received data sent to a host from a plurality of received packets. The flow control scheduler receives a plurality of transmitting requests corresponding to the ports from the host, arbitrates between the transmitting requests corresponding to the ports to select a transmitting port from the ports, receives a plurality of receiving requests corresponding to the ports from the host, and arbitrates between the plurality of receiving requests corresponding to the ports to select a receiving port from the ports. The port switch sends the transmitted packets to the transmitting port, and receives the received packets from the receiving port.

Abstract translation: 本发明提供一种电子设备。 在一个实施例中，电子设备包括多个端口，以太网电路，端口开关和流控制调度器。 以太网电路根据从主机发送的发送数据生成多个发送的分组，并从多个接收到的分组中导出发送给主机的接收数据。 流控制调度器从主机接收与该端口相对应的多个发送请求，在与端口对应的发送请求之间进行仲裁，从端口选择发送端口，从主机接收与该端口对应的多个接收请求， 并在与端口对应的多个接收请求之间进行仲裁，从端口选择接收端口。 端口交换机将发送的报文发送到发送端口，并从接收端口接收收到的报文。

公开(公告)号：US08724621B2

公开(公告)日：2014-05-13

申请号：US13232717

申请日：2011-09-14

Applicant: Chu-Ming Lin ,  Chih-Peng Chang

Inventor： Chu-Ming Lin ,  Chih-Peng Chang

IPC: H04L12/66

CPC classification number: H04L49/351

Abstract: The invention provides an electronic apparatus. In one embodiment, the electronic apparatus comprises a plurality of ports, an Ethernet circuit, a port switch, and a flow control scheduler. The Ethernet circuit generates a plurality of transmitted packets according to transmitted data sent from the host, and derives received data sent to a host from a plurality of received packets. The flow control scheduler receives a plurality of transmitting requests corresponding to the ports from the host, arbitrates between the transmitting requests corresponding to the ports to select a transmitting port from the ports, receives a plurality of receiving requests corresponding to the ports from the host, and arbitrates between the plurality of receiving requests corresponding to the ports to select a receiving port from the ports. The port switch sends the transmitted packets to the transmitting port, and receives the received packets from the receiving port.

Abstract translation: 本发明提供一种电子设备。 在一个实施例中，电子设备包括多个端口，以太网电路，端口开关和流控制调度器。 以太网电路根据从主机发送的发送数据生成多个发送的分组，并从多个接收到的分组中导出发送给主机的接收数据。 流控制调度器从主机接收与该端口相对应的多个发送请求，在与端口对应的发送请求之间进行仲裁，从端口选择发送端口，从主机接收与该端口对应的多个接收请求， 并在与端口对应的多个接收请求之间进行仲裁，从端口选择接收端口。 端口交换机将发送的报文发送到发送端口，并从接收端口接收收到的报文。

公开(公告)号：US07228368B2

公开(公告)日：2007-06-05

申请号：US10864200

申请日：2004-06-09

Applicant: Chu-Ming Lin ,  Shih-Chung Yin

Inventor： Chu-Ming Lin ,  Shih-Chung Yin

IPC: G06F13/36

CPC classification number: G06F13/385 ,  G06F13/426

Abstract: A polling-based communication apparatus and system. The apparatus of the invention, connected to a host computer through a peripheral bus, comprises an arbiter and multiple addressable entities. Each addressable entity corresponds to one of queues maintained in the host computer. The arbiter can determine which queue is to be served next in accordance with a quality of serve policy. The host computer polls each addressable entity by issuing a query packet. Depending on the queue chosen to be served next, the arbiter grants the corresponding addressable entity access to the peripheral bus, causing this granted addressable entity to respond to the host computer's polling with an acknowledgement packet. Thus the host computer initiates transactions to transfer data packets from the chosen queue through the peripheral bus to the corresponding addressable entity.

Abstract translation: 一种基于轮询的通信设备和系统。 通过外围总线连接到主计算机的本发明的装置包括仲裁器和多个可寻址实体。 每个可寻址实体对应于主计算机中维护的一个队列。 仲裁者可以根据服务质量确定下一个服务队列。 主机通过发出查询数据包来轮询每个可寻址实体。 根据选择接下来服务的队列，仲裁器授予相应的可寻址实体对外围总线的访问，使该授权的可寻址实体用确认分组对主计算机的轮询作出响应。 因此，主计算机启动事务以将数据分组从所选择的队列通过外围总线传送到相应的可寻址实体。

公开(公告)号：US20090259786A1

公开(公告)日：2009-10-15

申请号：US12339072

申请日：2008-12-19

Applicant: Chu-Ming Lin ,  Chien-Kuang Lin ,  Chuan-Hung Wang ,  Chin-Tai Liu

Inventor： Chu-Ming Lin ,  Chien-Kuang Lin ,  Chuan-Hung Wang ,  Chin-Tai Liu

IPC: G06F13/40

CPC classification number: G06F13/4027

Abstract: In a host-slave data transfer system, the slave device transmits data regarding its status and buffer conditions to the host using tailers inserted into the data being transferred to the host. The slave device has a plurality of buffers, a buffer management circuit which manages the buffers and obtains buffer condition information (e.g. amount of available buffer space, amount of buffered data to be transferred to the host), a detection circuit which collects interrupt status of the slave, a processing circuit which generates headers or tailers containing the buffer conditions information and interrupt status, and a merging circuit which merges multiple data segments received from the data-source/data-destination device and associated headers and tailers to generate a stream of merged data. The host obtains the buffer condition information from the tailers, and uses it to determine the amount of data to transmit or receive from the slave.

Abstract translation: 在主从数据传输系统中，从设备使用插入到正在传送给主机的数据中的分机向宿主发送关于其状态和缓冲器条件的数据。 从设备具有多个缓冲器，缓冲器管理电路管理缓冲器并获得缓冲器条件信息（例如可用缓冲器空间量，要传送到主机的缓冲数据量），检测电路，其收集中断状态 从设备，产生包含缓冲器条件信息和中断状态的报头或分机的处理电路，以及合并电路，其合并从数据源/数据 - 目的地设备和相关联的报头和分配器接收的多个数据段，以产生流 合并数据。 主机从尾随机获取缓冲条件信息，并使用它来确定从从站发送或接收的数据量。

公开(公告)号：US20080130651A1

公开(公告)日：2008-06-05

申请号：US11968340

申请日：2008-01-02

Applicant: Chu-Ming Lin

Inventor： Chu-Ming Lin

IPC: H04L12/56

CPC classification number: H04L49/901 ,  H04L47/10 ,  H04L47/2441 ,  H04L47/50 ,  H04L49/90

Abstract: A multi-queue single-FIFO scheme for quality of service oriented communication. According to the invention, an arbiter maintains a number of next access pointers for multiple queues storing data packets to be transmitted. The arbiter also determines which queue is to be serviced next contingent upon a quality of service policy and then fetches at least one data packet, identified by the chosen queue's next access pointer, through a peripheral bus by means of direct memory access (DMA). A single FIFO buffer is connected to the arbiter to store and manage the fetched data packet in a first-in-first-out manner. Following the FIFO buffer, physical layer interface logic accepts each data packet, if available, and prepares the data packet for transmission on a physical medium.

Abstract translation: 一种多队列单FIFO方案，用于面向服务的通信质量。 根据本发明，仲裁器维护多个用于存储要发送的数据分组的多个队列的下一个访问指针。 仲裁器还根据服务质量策略确定下一个服务队列，然后通过外部总线通过直接存储器访问（DMA）获取由所选择的队列的下一个访问指针识别的至少一个数据包。 单个FIFO缓冲器连接到仲裁器，以先入先出的方式存储和管理提取的数据包。 在FIFO缓冲器之后，物理层接口逻辑接收每个数据包（如果可用），并且准备数据包以在物理介质上传输。

公开(公告)号：US07218628B2

公开(公告)日：2007-05-15

申请号：US10209489

申请日：2002-07-29

Applicant: Mao-Ching Chiu ,  Chu-Ming Lin ,  Po-Hung Chen ,  Chin-Wen Lin ,  Tai-Yuan Cheng

Inventor： Mao-Ching Chiu ,  Chu-Ming Lin ,  Po-Hung Chen ,  Chin-Wen Lin ,  Tai-Yuan Cheng

IPC: H04J3/24

CPC classification number: H04W99/00 ,  H04L7/042

Abstract: A method and a device for detecting a preamble type of a wireless data frame are provided. The preamble has a synchronization (SYNC) field and a start frame delimiter (SFD) field, and the method comprises following steps. The wireless data frame is first received, and then determined whether the wireless data frame has a short preamble. When the wireless data frame has the short preamble, the wireless data frame is transmitted to a MAC device. In addition, if the wireless data frame does not have the short preamble, it determines whether the wireless data frame has a long preamble. When the wireless data frame has the long preamble, the wireless data frame is then transmitted to the MAC device.

Abstract translation: 提供了一种用于检测无线数据帧的前同步码类型的方法和装置。 前导码具有同步（SYNC）字段和起始帧分隔符（SFD）字段，并且该方法包括以下步骤。 首先接收无线数据帧，然后确定无线数据帧是否具有短前导码。 当无线数据帧具有短前导码时，无线数据帧被发送到MAC设备。 此外，如果无线数据帧不具有短前导码，则它确定无线数据帧是否具有长前导码。 当无线数据帧具有长的前导码时，无线数据帧然后被发送到MAC设备。

公开(公告)号：US20050157709A1

公开(公告)日：2005-07-21

申请号：US10760654

申请日：2004-01-20

Applicant: Chu-Ming Lin

Inventor： Chu-Ming Lin

IPC: H04L12/56 ,  H04L12/50

CPC classification number: H04L49/901 ,  H04L47/10 ,  H04L47/2441 ,  H04L47/50 ,  H04L49/90

Abstract: A multi-queue single-FIFO scheme for quality of service oriented communication. According to the invention, an arbiter maintains a number of next access pointers for multiple queues storing data packets to be transmitted. The arbiter also determines which queue is to be serviced next contingent upon a quality of service policy and then fetches at least one data packet, identified by the chosen queue's next access pointer, through a peripheral bus by means of direct memory access (DMA). A single FIFO buffer is connected to the arbiter to store and manage the fetched data packet in a first-in-first-out manner. Following the FIFO buffer, physical layer interface logic accepts each data packet, if available, and prepares the data packet for transmission on a physical medium.

Abstract translation: 一种多队列单FIFO方案，用于面向服务的通信质量。 根据本发明，仲裁器维护多个用于存储要发送的数据分组的多个队列的下一个访问指针。 仲裁器还根据服务质量策略确定下一个服务队列，然后通过外部总线通过直接存储器访问（DMA）获取由所选择的队列的下一个访问指针识别的至少一个数据包。 单个FIFO缓冲器连接到仲裁器，以先入先出的方式存储和管理提取的数据包。 在FIFO缓冲器之后，物理层接口逻辑接收每个数据包（如果可用），并且准备数据包以在物理介质上传输。

公开(公告)号：US08867344B2

公开(公告)日：2014-10-21

申请号：US12407186

申请日：2009-03-19

Applicant: Chuan-Hung Wang ,  Chien-Kuang Lin ,  Chin-Tai Liu ,  Chu-Ming Lin

Inventor： Chuan-Hung Wang ,  Chien-Kuang Lin ,  Chin-Tai Liu ,  Chu-Ming Lin

IPC: H04L12/26 ,  H04L12/801 ,  H04L12/861 ,  H04L1/18

CPC classification number: H04L47/10 ,  G06F11/0745 ,  G06F11/0793 ,  G06F11/1004 ,  H04L1/0052 ,  H04L1/0061 ,  H04L1/188 ,  H04L49/90 ,  H04L2001/0094

Abstract: A method for data transmission in a device coupled to a host via a bus is provided. A sequence of data packets are received from the host and the received data packets are stored into a buffering unit of the device. It is then determined whether a predetermined error has occurred. When the predetermined error has occurred, the buffering unit of the device is locked to stop receiving the data packets. Thereafter, the buffering unit of the device is unlocked according to an unlock request from the host to resume receiving subsequent data packets.

Abstract translation: 提供了一种通过总线耦合到主机的设备中的数据传输方法。 从主机接收到数据分组序列，并将接收的数据分组存储到设备的缓冲单元中。 然后确定是否发生了预定的错误。 当发生预定错误时，设备的缓冲单元被锁定以停止接收数据分组。 此后，设备的缓冲单元根据来自主机的解锁请求解锁，以恢复接收后续数据分组。

公开(公告)号：US20110276730A1

公开(公告)日：2011-11-10

申请号：US12773660

申请日：2010-05-04

Applicant: Chu-Ming Lin ,  Chiao-Chi Huang ,  Chien-Kuang LIN ,  Yu-Tin Hsu

Inventor： Chu-Ming Lin ,  Chiao-Chi Huang ,  Chien-Kuang LIN ,  Yu-Tin Hsu

IPC: G06F3/00 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F2213/3808 ,  H04L49/9015

Abstract: In a host-slave data transfer system, the slave device receives packet based data from an external device and stores the packet content in a buffer as data segments. The slave merges a plurality of data segments into data streams and transmits the data streams to the host. The host uses direct memory access (DMA) to unpack the data stream from the slave into individual data segments without memory copy. To enable the host to set up DMA, the slave transmits information regarding sizes of the data segments to the host beforehand via an outband channel, e.g. by transmitting the size information in headers and/or tailers inserted into previous data streams. The host utilizes the data segment size information to program descriptor tables, such that each descriptor in the descriptor tables causes one data segment in the data stream to be stored in the system memory of the host.

Abstract translation: 在主从数据传输系统中，从设备从外部设备接收基于分组的数据，并将分组内容作为数据段存储在缓冲器中。 从机将多个数据段合并成数据流，并将数据流发送到主机。 主机使用直接存储器访问（DMA）将数据流从从属设备解包到单独的数据段，而无需存储器复制。 为了使主机能够建立DMA，从机通过带外频道预先向主机发送关于数据段大小的信息，例如。 通过在插入到先前的数据流中的头部和/或分割器中传送大小信息。 主机利用数据段大小信息来编程描述符表，使得描述符表中的每个描述符使得数据流中的一个数据段被存储在主机的系统存储器中。

公开(公告)号：US07912077B2

公开(公告)日：2011-03-22

申请号：US11968340

申请日：2008-01-02

Applicant: Chu-Ming Lin

Inventor： Chu-Ming Lin

IPC: H04L12/28

CPC classification number: H04L49/901 ,  H04L47/10 ,  H04L47/2441 ,  H04L47/50 ,  H04L49/90

Abstract: A multi-queue single-FIFO scheme for quality of service oriented communication. According to the invention, an arbiter maintains a number of next access pointers for multiple queues storing data packets to be transmitted. The arbiter also determines which queue is to be serviced next contingent upon a quality of service policy and then fetches at least one data packet, identified by the chosen queue's next access pointer, through a peripheral bus by means of direct memory access (DMA). A single FIFO buffer is connected to the arbiter to store and manage the fetched data packet in a first-in-first-out manner. Following the FIFO buffer, physical layer interface logic accepts each data packet, if available, and prepares the data packet for transmission on a physical medium.

Abstract translation: 一种多队列单FIFO方案，用于面向服务的通信质量。 根据本发明，仲裁器维护多个用于存储要发送的数据分组的多个队列的下一个访问指针。 仲裁器还根据服务质量策略确定下一个服务队列，然后通过外部总线通过直接存储器访问（DMA）获取由所选择的队列的下一个访问指针识别的至少一个数据包。 单个FIFO缓冲器连接到仲裁器，以先入先出的方式存储和管理提取的数据包。 在FIFO缓冲器之后，物理层接口逻辑接收每个数据包（如果可用），并且准备数据包以在物理介质上传输。