公开(公告)号：US20060008987A1

公开(公告)日：2006-01-12

申请号：US11217624

申请日：2005-09-01

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

公开(公告)号：US20050104114A1

公开(公告)日：2005-05-19

申请号：US10714752

申请日：2003-11-17

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/48 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

摘要翻译： 描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。 使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。 通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。 低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

公开(公告)号：US20060009035A1

公开(公告)日：2006-01-12

申请号：US11218099

申请日：2005-09-01

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/44

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

公开(公告)号：US20060008989A1

公开(公告)日：2006-01-12

申请号：US11217946

申请日：2005-09-01

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

公开(公告)号：US07569468B2

公开(公告)日：2009-08-04

申请号：US11217624

申请日：2005-09-01

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/3205

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

摘要翻译： 描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。 使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。 通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。 低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

公开(公告)号：US20060008963A1

公开(公告)日：2006-01-12

申请号：US11217950

申请日：2005-09-01

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

公开(公告)号：US20060006455A1

公开(公告)日：2006-01-12

申请号：US11218100

申请日：2005-09-01

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L29/788 ,  H01L23/52

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

摘要翻译： 描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。 使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。 通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。 低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

公开(公告)号：US20050242390A1

公开(公告)日：2005-11-03

申请号：US11174675

申请日：2005-07-05

申请人： Chun Chen ,  Graham Wolstenholme

发明人： Chun Chen ,  Graham Wolstenholme

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L27/115

摘要： An embodiment of a floating-gate memory cell has a tunnel dielectric layer formed overlying a semiconductor substrate; a drain region formed in a semiconductor substrate adjacent a first side of the tunnel dielectric layer, a source region formed in a semiconductor substrate adjacent a second side of the tunnel dielectric layer, a floating-gate layer formed overlying the tunnel dielectric layer, a control-gate layer formed overlying the floating-gate layer, and an intergate dielectric layer formed interposed between the floating-gate layer and the control gate layer. The control-gate layer includes a silicide layer in contact with an underlying polysilicon layer. There is no interposing dielectric layer between the control-gate layer and an overlying bulk insulator layer, and a width of the silicide layer is substantially equal to a width of the polysilicon layer.

摘要翻译： 浮栅存储单元的实施例具有形成在半导体衬底上的隧道电介质层; 形成在与隧道介电层的第一侧相邻的半导体衬底中的漏极区域，形成在与隧道介电层的第二侧相邻的半导体衬底中的源极区域，形成在隧道介电层上的浮动栅极层，控制层 形成在浮置栅极层上的栅极层以及介于浮置栅极层与控制栅极层之间的隔间介电层。 控制栅极层包括与下面的多晶硅层接触的硅化物层。 在控制栅极层和上覆体积绝缘体层之间没有中介电介质层，并且硅化物层的宽度基本上等于多晶硅层的宽度。

公开(公告)号：US20050009272A1

公开(公告)日：2005-01-13

申请号：US10602324

申请日：2003-06-24

申请人： Chun Chen ,  Graham Wolstenholme

发明人： Chun Chen ,  Graham Wolstenholme

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L27/115

摘要： Concurrently formed self-aligned suicides on word lines and contacts of a memory device facilitate reduced resistance and/or reduced device sizing. The word-line suicide is formed at a stage significantly later than in standard processing, decreasing concerns of thermal stability of the silicide, thus allowing the use of lower-resistance silicides. In addition, by forming contacts to drain and/or source regions prior to forming the silicide for the word lines, aspect ratios for the contact holes or trenches are reduced for a given pitch, thus improving effectiveness of processing to remove material from these holes and trenches or allowing the use of a smaller pitch. By providing a process for the application of a silicide in array source interconnects, a single array source interconnect can couple an entire row of memory cells, thereby reducing the number of contacts made to an array ground.

摘要翻译： 在记录装置的字线和触点上同时形成的自对准自杀有利于减少阻力和/或减小装置尺寸。 字线自杀在比标准处理中明显晚的阶段形成，减少了对硅化物的热稳定性的关注，从而允许使用较低电阻的硅化物。 此外，通过在形成用于字线的硅化物之前形成与漏极和/或源极区的接触，对于给定的间距，接触孔或沟槽的纵横比减小，从而提高了从这些孔移除材料的处理的有效性， 沟槽或允许使用较小的间距。 通过提供在阵列源互连中应用硅化物的过程，单个阵列源互连可以耦合整行存储器单元，从而减少对阵列地阵进行的触点的数量。

公开(公告)号：US07271438B2

公开(公告)日：2007-09-18

申请号：US11174675

申请日：2005-07-05

申请人： Chun Chen ,  Graham Wolstenholme

发明人： Chun Chen ,  Graham Wolstenholme

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L27/115

摘要： An embodiment of a floating-gate memory cell has a tunnel dielectric layer formed overlying a semiconductor substrate; a drain region formed in a semiconductor substrate adjacent a first side of the tunnel dielectric layer, a source region formed in a semiconductor substrate adjacent a second side of the tunnel dielectric layer, a floating-gate layer formed overlying the tunnel dielectric layer, a control-gate layer formed overlying the floating-gate layer, and an intergate dielectric layer formed interposed between the floating-gate layer and the control gate layer. The control-gate layer includes a silicide layer in contact with an underlying polysilicon layer. There is no interposing dielectric layer between the control-gate layer and an overlying bulk insulator layer, and a width of the silicide layer is substantially equal to a width of the polysilicon layer.

摘要翻译： 浮栅存储单元的实施例具有形成在半导体衬底上的隧道电介质层; 形成在与隧道介电层的第一侧相邻的半导体衬底中的漏极区域，形成在与隧道介电层的第二侧相邻的半导体衬底中的源极区域，形成在隧道介电层上的浮动栅极层，控制层 形成在浮置栅极层上的栅极层以及介于浮置栅极层与控制栅极层之间的隔间介电层。 控制栅极层包括与下面的多晶硅层接触的硅化物层。 在控制栅极层和上覆体积绝缘体层之间没有中介电介质层，并且硅化物层的宽度基本上等于多晶硅层的宽度。