公开(公告)号：US20050094700A1

公开(公告)日：2005-05-05

申请号：US10975365

申请日：2004-10-29

申请人： Chun-Hung Ko ,  Hsin-Yueh Sung

发明人： Chun-Hung Ko ,  Hsin-Yueh Sung

IPC分类号： G02B27/09 ,  G02F2/00 ,  H01S3/08

CPC分类号： G02B19/0009 ,  G02B19/0052 ,  G02B27/0944

摘要： A apparatus for generating a structured line having a sinusoidal intensity distribution is disclosed. The apparatus comprises a coherent light source and a diffractive optical element. The coherent light source provides an incident light beam to the diffractive optical element, the incident light beam being modulated by means of the diffractive optical element to form a fringe pattern of sinusoidal intensity distribution. The diffractive optical element design is optimized in accordance with the optical field distribution of an incident-light-beam plane and the optical field distribution of an output-light-beam plane.

摘要翻译： 公开了一种用于产生具有正弦强度分布的结构化线的装置。 该装置包括相干光源和衍射光学元件。 相干光源向衍射光学元件提供入射光束，入射光束借助于衍射光学元件进行调制，以形成正弦强度分布的条纹图案。 衍射光学元件设计根据入射光束平面的光场分布和输出光束平面的光场分布进行优化。

公开(公告)号：US20130056830A1

公开(公告)日：2013-03-07

申请号：US13224896

申请日：2011-09-02

申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

IPC分类号： H01L29/78 ,  H01L21/76

CPC分类号： H01L21/76227 ,  H01L21/823437 ,  H01L27/0694 ,  H01L27/11

摘要： An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.

摘要翻译： 一个实施例是半导体结构。 半导体结构在衬底上包括至少两个栅极结构。 栅极结构在栅极结构之间限定凹陷，并且凹部由垂直方向上的深度限定。 深度是从至少一个栅极结构的顶表面到衬底的顶表面之下的深度，并且深度在衬底中的隔离区域中延伸。 半导体结构还包括在凹部中的填充材料。 填充材料在垂直方向上具有第一厚度。 该半导体结构还包括在凹槽中和填充材料之上的层间电介质层。 所述层间电介质层在所述至少一个栅极结构的顶表面的垂直方向上具有第二厚度。 第一厚度大于第二厚度。

公开(公告)号：US08877614B2

公开(公告)日：2014-11-04

申请号：US13272875

申请日：2011-10-13

申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/20 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L21/76834 ,  H01L21/76897 ,  H01L29/66628 ,  H01L29/66636

摘要： An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1.

摘要翻译： 一个实施例是半导体结构。 半导体结构包括外延区域，栅极结构，接触间隔物和蚀刻停止层。 外延区域在衬底中。 外延区的顶表面从衬底的顶表面升高，并且外延区具有在衬底的顶表面和外延区的顶表面之间的刻面。 栅极结构在衬底上。 接触间隔物横向在外延区域的小面和栅极结构之间。 蚀刻停止层在每个接触间隔物和外延区域的顶表面之上并相邻。 接触间隔物的蚀刻选择性与蚀刻停止层的蚀刻选择性的比率等于或小于3:1。

公开(公告)号：US08692353B2

公开(公告)日：2014-04-08

申请号：US13224896

申请日：2011-09-02

申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

IPC分类号： H01L29/06

CPC分类号： H01L21/76227 ,  H01L21/823437 ,  H01L27/0694 ,  H01L27/11

摘要： An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.

摘要翻译： 一个实施例是半导体结构。 半导体结构在衬底上包括至少两个栅极结构。 栅极结构在栅极结构之间限定凹陷，并且凹部由垂直方向上的深度限定。 深度是从至少一个栅极结构的顶表面到衬底的顶表面之下的深度，并且深度在衬底中的隔离区域中延伸。 半导体结构还包括在凹部中的填充材料。 填充材料在垂直方向上具有第一厚度。 该半导体结构还包括在凹槽中和填充材料之上的层间电介质层。 所述层间电介质层在所述至少一个栅极结构的顶表面的垂直方向上具有第二厚度。 第一厚度大于第二厚度。

公开(公告)号：US06995902B2

公开(公告)日：2006-02-07

申请号：US10692754

申请日：2003-10-27

申请人： Hau-Wei Wang ,  Spring Ying-Cheun Yeh ,  Chun-Hung Ko

发明人： Hau-Wei Wang ,  Spring Ying-Cheun Yeh ,  Chun-Hung Ko

IPC分类号： G02B21/06

CPC分类号： G02B5/1866 ,  G02B21/082

摘要： A microscopic imaging apparatus with flat-top distribution of light is disclosed, which includes an incident light source, a diffractive optical element, a beam-splitter, a tunable filter and an image sensor. The diffractive optical element receives an incident light provided by the incident light source and generates a uniform incident light. The uniform incident light illuminates a sample so that an optical signal is emitted from the sample. The optical signal passes through the beam-splitter and the filter unit to reach the image sensor for obtaining the detected image of the sample.

摘要翻译： 公开了一种具有平顶分布的光的显微成像装置，其包括入射光源，衍射光学元件，分束器，可调谐滤光器和图像传感器。 衍射光学元件接收由入射光源提供的入射光并产生均匀的入射光。 均匀入射光照射样品，从而从样品发射光信号。 光信号通过光束分离器和滤光器单元以到达图像传感器以获得检测到的样本图像。

公开(公告)号：US08735258B2

公开(公告)日：2014-05-27

申请号：US13343903

申请日：2012-01-05

申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Shyh-Wei Wang

发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Shyh-Wei Wang

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L21/02 ,  H01L21/20 ,  H01L27/0629 ,  H01L28/20

摘要： Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate.

摘要翻译： 提供了制造包括金属栅极晶体管和电阻器的半导体器件的方法。 一种方法包括提供包括晶体管器件区域和隔离区域的衬底，在晶体管器件区域上形成虚拟栅极，在隔离区域上形成电阻器，以及用掺杂剂注入电阻器。 该方法还包括湿式蚀刻伪栅极以去除虚拟栅极，然后在晶体管器件区域上形成金属栅极以替代伪栅极。

公开(公告)号：US20130178039A1

公开(公告)日：2013-07-11

申请号：US13343903

申请日：2012-01-05

申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Shyh-Wei Wang

发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Shyh-Wei Wang

IPC分类号： H01L21/02

CPC分类号： H01L21/02 ,  H01L21/20 ,  H01L27/0629 ,  H01L28/20

摘要： Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate.

摘要翻译： 提供了制造包括金属栅极晶体管和电阻器的半导体器件的方法。 一种方法包括提供包括晶体管器件区域和隔离区域的衬底，在晶体管器件区域上形成虚拟栅极，在隔离区域上形成电阻器，以及用掺杂剂注入电阻器。 该方法还包括湿式蚀刻伪栅极以去除虚拟栅极，然后在晶体管器件区域上形成金属栅极以替代伪栅极。

公开(公告)号：US20130092985A1

公开(公告)日：2013-04-18

申请号：US13272875

申请日：2011-10-13

申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L21/76834 ,  H01L21/76897 ,  H01L29/66628 ,  H01L29/66636

摘要： An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1.

摘要翻译： 一个实施例是半导体结构。 半导体结构包括外延区域，栅极结构，接触间隔物和蚀刻停止层。 外延区域在衬底中。 外延区的顶表面从衬底的顶表面升高，并且外延区具有在衬底的顶表面和外延区的顶表面之间的刻面。 栅极结构在衬底上。 接触间隔物横向在外延区域的小面和栅极结构之间。 蚀刻停止层在每个接触间隔物和外延区域的顶表面之上并相邻。 接触间隔物的蚀刻选择性与蚀刻停止层的蚀刻选择性的比率等于或小于3:1。