公开(公告)号：US20230178419A1

公开(公告)日：2023-06-08

申请号：US18103850

申请日：2023-01-31

Applicant: Applied Materials, Inc.

Inventor： Benjamin COLOMBEAU ,  Theresa Kramer GUARINI ,  Malcolm BEVAN ,  Rui CHENG

IPC: H01L21/762 ,  H01L21/02 ,  H01J37/32 ,  C23C16/56 ,  C23C16/24 ,  C23C16/28 ,  C23C16/50

CPC classification number: H01L21/76227 ,  H01L21/02247 ,  H01L21/02252 ,  H01J37/32743 ,  H01J37/32788 ,  C23C16/56 ,  C23C16/24 ,  C23C16/28 ,  C23C16/50 ,  H01J37/32816 ,  H01J2237/332

Abstract: Generally, examples described herein relate to methods and processing systems for forming isolation structures (e.g., shallow trench isolations (STIs)) between fins on a substrate. In an example, fins are formed on a substrate. A liner layer is conformally formed on and between the fins. Forming the liner layer includes conformally depositing a pre-liner layer on and between the fins, and densifying, using a plasma treatment, the pre-liner layer to form the liner layer. A dielectric material is formed on the liner layer.

公开(公告)号：US10084040B2

公开(公告)日：2018-09-25

申请号：US15290772

申请日：2016-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Chun Huang ,  Bor Chiuan Hsieh ,  Pei-Ren Jeng ,  Tai-Chun Huang ,  Tze-Liang Lee

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/0649 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/324 ,  H01L21/76227 ,  H01L29/66795

Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

公开(公告)号：US20180166352A1

公开(公告)日：2018-06-14

申请号：US15673248

申请日：2017-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Min Choi ,  Dong Ryul Lee ,  Ho Ouk Lee ,  Ji Young Kim ,  Chang Hyun Cho

IPC: H01L23/14 ,  H01L21/762

CPC classification number: H01L23/147 ,  H01L21/76205 ,  H01L21/76227 ,  H01L21/76229 ,  H01L27/10894

Abstract: A semiconductor device includes a substrate having a semiconductor layer. A trench is formed within the semiconductor layer. A filling insulating film is disposed within the trench. An insertion liner is disposed within the filling insulating film. The insertion liner is spaced apart from the semiconductor layer and extends along the bottom surface of the trench.

公开(公告)号：US09613848B2

公开(公告)日：2017-04-04

申请号：US14621082

申请日：2015-02-12

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/76227 ,  H01L21/02129 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76801 ,  H01L21/76804

Abstract: A method for forming a dielectric structure includes forming an auxiliary layer over a substrate, and forming a hole within the auxiliary layer. A fill material is deposited into the hole. The auxiliary layer is removed to form the dielectric structure having a negative taper. The dielectric structure has a top critical dimension greater than a bottom critical dimension.

公开(公告)号：US09559134B2

公开(公告)日：2017-01-31

申请号：US14564196

申请日：2014-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Jung-I Lin ,  Ta-Chun Lin ,  Tien-Lu Lin ,  Chen-Jong Wang

IPC: H01L27/148 ,  H01L29/768 ,  H01L29/00 ,  H01L27/146 ,  H01L27/092 ,  H01L29/94 ,  H01L27/12

CPC classification number: H01L21/764 ,  H01L21/76224 ,  H01L21/76227 ,  H01L21/76289 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/0921 ,  H01L27/1203 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L29/945

Abstract: An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided.

Abstract translation: 提供了采用深沟槽间隔隔离的图像传感器。 多个像素传感器布置在半导体衬底之上或之内。 沟槽在多个像素传感器周围和相邻的像素传感器之间并且在半导体衬底中布置，并且沟槽在沟槽的侧壁之间具有间隙。 在覆盖间隙的位置处，在沟槽之上或之内布置盖。 盖子密封沟槽内的间隙。 还提供了一种制造图像传感器的方法。

公开(公告)号：US09406544B1

公开(公告)日：2016-08-02

申请号：US14737760

申请日：2015-06-12

Applicant: LAM RESEARCH CORPORATION

Inventor： Wei Tang ,  Jason Daejin Park ,  Bart Van Schravendijk ,  Kaihan Ashtiani

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/324 ,  H01L29/06

CPC classification number: H01L21/02271 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/76227

Abstract: A method for filling a trench in a substrate includes partially filling the trench with a first silicon dioxide layer. An amorphous silicon layer is deposited on the silicon dioxide layer. The trench is filled with a second silicon dioxide layer. An oxidation treatment is performed on the substrate to oxidize the amorphous silicon layer.

Abstract translation: 用于在衬底中填充沟槽的方法包括用第一二氧化硅层部分地填充沟槽。 非晶硅层沉积在二氧化硅层上。 沟槽填充有第二二氧化硅层。 在基板上进行氧化处理以氧化非晶硅层。

公开(公告)号：US08921183B2

公开(公告)日：2014-12-30

申请号：US12962655

申请日：2010-12-08

Applicant: Jen-Jui Huang ,  Hung-Ming Tsai

Inventor： Jen-Jui Huang ,  Hung-Ming Tsai

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76227

Abstract: A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench.

Abstract translation: 描述了一种用于制造沟槽隔离结构的方法。 在衬底中形成沟槽。 至少在沟槽中形成衬垫层。 至少在沟槽的侧壁上形成前体层。 前体层被转换成具有比前体层更大的体积并填充沟槽的绝缘层。

公开(公告)号：US08835242B2

公开(公告)日：2014-09-16

申请号：US14179103

申请日：2014-02-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

IPC: H01L21/762

CPC classification number: H01L21/76227 ,  H01L21/823437 ,  H01L27/0694 ,  H01L27/11

Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.

公开(公告)号：US20140162432A1

公开(公告)日：2014-06-12

申请号：US14179103

申请日：2014-02-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

IPC: H01L21/762

CPC classification number: H01L21/76227 ,  H01L21/823437 ,  H01L27/0694 ,  H01L27/11

Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.

Abstract translation: 一个实施例是半导体结构。 半导体结构在衬底上包括至少两个栅极结构。 栅极结构在栅极结构之间限定凹陷，并且凹部由垂直方向上的深度限定。 深度是从至少一个栅极结构的顶表面到衬底的顶表面之下的深度，并且深度在衬底中的隔离区域中延伸。 半导体结构还包括在凹部中的填充材料。 填充材料在垂直方向上具有第一厚度。 该半导体结构还包括在凹槽中和填充材料之上的层间电介质层。 所述层间电介质层在所述至少一个栅极结构的顶表面的垂直方向上具有第二厚度。 第一厚度大于第二厚度。

公开(公告)号：US20120282777A1

公开(公告)日：2012-11-08

申请号：US13102506

申请日：2011-05-06

Applicant: Shing-Yih SHIH ,  Yi-Nan CHEN ,  Hsien-Wen LIU

Inventor： Shing-Yih SHIH ,  Yi-Nan CHEN ,  Hsien-Wen LIU

IPC: H01L21/302 ,  H01L21/31

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02307 ,  H01L21/02326 ,  H01L21/3105 ,  H01L21/76227

Abstract: A method for increasing adhesion between polysilazane and silicon nitride is disclosed, comprising, providing a substrate comprising a trench, forming a silicon nitride liner layer on a bottom surface and a sidewall of the trench, performing a treating process to the silicon nitride liner layer for producing a hydrophilic surface with OH groups that can increase adhesion between the silicon nitride liner layer and a subsequently formed polysilazane coating layer, and forming a polysilazane coating layer into the trench and on the silicon nitride liner layer.

Abstract translation: 公开了一种用于增加聚硅氮烷和氮化硅之间的粘合性的方法，包括：提供包括沟槽的衬底，在沟槽的底表面和侧壁上形成氮化硅衬垫层，对氮化硅衬垫层执行处理工艺 产生具有OH基团的亲水表面，其可以增加氮化硅衬垫层和随后形成的聚硅氮烷涂层之间的粘附性，以及在沟槽和氮化硅衬垫层中形成聚硅氮烷涂层。