公开(公告)号：US12125788B2

公开(公告)日：2024-10-22

申请号：US18386497

申请日：2023-11-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Saehan Park ,  Hoonseok Seo ,  Gil Hwan Son ,  Byounghak Hong ,  Kang Ill Seo

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532 ,  H01L27/06

CPC分类号： H01L23/5286 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L27/0694 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

摘要： Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.

公开(公告)号：US12062658B2

公开(公告)日：2024-08-13

申请号：US17385634

申请日：2021-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Lien Huang

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/528 ,  H01L27/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/0694 ,  H01L29/0843 ,  H01L29/66795 ,  H01L29/7851

摘要： An integrated circuit structure includes a lower interconnect structure, a first semiconductor fin, a lower gate structure, first source/drain structures, an upper gate structure, and an upper interconnect structure. The first semiconductor fin is above the lower interconnect structure. The lower gate structure is under the first semiconductor fin and extends across the first semiconductor fin. The first source/drain structures are in the first semiconductor fin and on opposite sides of the lower gate structure. The first source/drain structures forms a lower transistor with the lower gate structure. The upper gate structure is above the first semiconductor fin and extends across the first semiconductor fin. The upper gate structure forms an upper transistor with the first source/drain structures. The upper interconnect structure is above the upper gate.

公开(公告)号：US12034002B2

公开(公告)日：2024-07-09

申请号：US17678040

申请日：2022-02-23

申请人： Innolux Corporation

发明人： Tang Chin Hung ,  Chin-Lung Ting ,  Chung-Kuang Wei ,  Ker-Yih Kao ,  Tong-Jung Wang ,  Chih-Yung Hsieh ,  Hao Jung Huang ,  I-Yin Li ,  Chia-Chi Ho ,  Yi Hung Lin ,  Cheng-Hsu Chou ,  Chia-Ping Tseng

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/93 ,  H01L23/538

CPC分类号： H01L27/0629 ,  H01L21/823475 ,  H01L23/5223 ,  H01L29/93 ,  H01L23/5385 ,  H01L27/0694

摘要： The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, and an electronic assembly. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer has an opening and is formed on the first surface. The second metal layer is formed on the second surface and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface. The electronic assembly is electrically connected with the first metal layer and the second metal layer.

公开(公告)号：US11769768B2

公开(公告)日：2023-09-26

申请号：US16889432

申请日：2020-06-01

申请人： Wolfspeed, Inc.

发明人： Terry Alcorn ,  Daniel Namishia ,  Fabian Radulescu

IPC分类号： H01L27/06 ,  H01L21/683 ,  H01L21/768 ,  H01L21/8258 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L27/0694 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/8258 ,  H01L23/481 ,  H01L23/498 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L27/0605 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/73257 ,  H01L2924/1421

摘要： An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.

公开(公告)号：US20180175034A1

公开(公告)日：2018-06-21

申请号：US15387501

申请日：2016-12-21

申请人： QUALCOMM Incorporated

发明人： Sinan GOKTEPELI ,  Jean RICHAUD

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L27/0924 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0694 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/42392

摘要： An integrated circuit device may include a p-type metal oxide semiconductor (PMOS) transistor supported by a backside of an isolation layer. The integrated circuit device may also include an n-type metal oxide semiconductor (NMOS) transistor supported by a front-side of the isolation layer, opposite the backside. The integrated circuit device may further include a shared contact extending through the isolation layer and electrically coupling a first terminal of the PMOS transistor to the first terminal of the NMOS transistor.

公开(公告)号：US20180166317A1

公开(公告)日：2018-06-14

申请号：US15882821

申请日：2018-01-29

申请人： Micron Technology, Inc.

发明人： Kyle K. Kirby ,  Kunal R. Parekh

IPC分类号： H01L21/74 ,  H01L29/66 ,  H01L21/265 ,  H01L21/768

CPC分类号： H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

摘要： Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US09954031B2

公开(公告)日：2018-04-24

申请号：US15186765

申请日：2016-06-20

申请人： Sony Corporation

发明人： Takashi Yokoyama ,  Taku Umebayashi

IPC分类号： H01L27/22 ,  H01L23/48 ,  H01L29/78 ,  H01L21/768 ,  H01L27/06 ,  H01L21/84 ,  H01L27/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC分类号： H01L27/228 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/84 ,  H01L21/845 ,  H01L23/481 ,  H01L27/0694 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/7833 ,  H01L29/785 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a semiconductor substrate with a first surface and a second surface facing each other, the semiconductor substrate having an element region in which a transistor is provided on the first surface, and a separation region in which an element separating layer surrounding the element region is provided; a contact plug extending from the first surface to the second surface, in the element region of the semiconductor substrate; and an insulating film covering a periphery of the contact plug.

公开(公告)号：US09953870B2

公开(公告)日：2018-04-24

申请号：US15488514

申请日：2017-04-16

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC分类号： H01L21/77 ,  H01L29/66 ,  H01L27/10 ,  H01L23/40 ,  H01L23/00 ,  H01L23/31 ,  H01L27/02 ,  B82Y10/00 ,  H01L21/84 ,  H01L23/528 ,  H01L21/683 ,  H01L21/762 ,  H01L27/06 ,  H01L29/78 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/10 ,  G11C16/04 ,  H01L23/36 ,  H01L23/367 ,  H01L27/088

CPC分类号： H01L21/77 ,  B82Y10/00 ,  G11C16/0408 ,  G11C16/0483 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4012 ,  H01L23/5286 ,  H01L24/01 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/249 ,  H01L28/00 ,  H01L29/1033 ,  H01L29/66257 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

公开(公告)号：US09947688B2

公开(公告)日：2018-04-17

申请号：US13528832

申请日：2012-06-20

申请人： James S. Cable ,  Anthony Mark Miscione ,  Ronald Eugene Reedy

发明人： James S. Cable ,  Anthony Mark Miscione ,  Ronald Eugene Reedy

IPC分类号： H01L21/00 ,  H01L21/36 ,  H01L21/20 ,  H01L27/12 ,  H01L27/06 ,  H01L21/78

CPC分类号： H01L27/1203 ,  H01L21/78 ,  H01L27/0694 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/11002 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/94 ,  H01L2924/15192 ,  H01L2224/11

摘要： Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.

公开(公告)号：US20180076145A1

公开(公告)日：2018-03-15

申请号：US15266972

申请日：2016-09-15

申请人： Qualcomm Incorporated

发明人： Sinan GOKTEPELI

IPC分类号： H01L23/544 ,  H01L27/12 ,  H01L21/683 ,  H01L21/84 ,  H01L21/762 ,  H01L27/13

CPC分类号： H01L23/544 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0694 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/1266 ,  H01L27/13 ,  H01L2221/6835

摘要： An integrated circuit structure may include an alignment column on a front-side surface of an isolation layer. The alignment column may extend through a backside surface opposite the front-side surface of the isolation layer. The integrated circuit structure may also include front-side transistors on the front-side surface of the isolation layer. The integrated circuit structure may further include backside transistors on the backside surface of the isolation layer. A first front-side transistor is aligned with a first backside transistor according to the alignment column.