公开(公告)号：US07173404B2

公开(公告)日：2007-02-06

申请号：US10915398

申请日：2004-08-11

Applicant: Chung Cheng Wu

Inventor： Chung Cheng Wu

IPC: G05F1/56

CPC classification number: H02M3/156 ,  Y10S323/901

Abstract: An auto-switching converter with PWM and PFM selection supplies a boosted DC power to a load through a power switch unit. A starter outputs a starting-enabling signal. An auto PWM/PFM controller is connected to the starter for outputting a selection signal. A controller and a PFM controller are connected to the auto PWM/PFM controller, the power switch unit and the load for transmitting a PWM control signal and a PFM control signal to the power switch unit, respectively, for controlling the switching action of the power switch unit.

Abstract translation: 具有PWM和PFM选择的自动切换转换器通过电源开关单元为负载提供升压直流电源。 起动器输出启动信号。 自动PWM / PFM控制器连接到起动器，用于输出选择信号。 控制器和PFM控制器分别连接到自动PWM / PFM控制器，电源开关单元和用于将PWM控制信号和PFM控制信号传输到电源开关单元的负载，用于控制电源的开关动作 开关单元。

公开(公告)号：US06770516B2

公开(公告)日：2004-08-03

申请号：US10235253

申请日：2002-09-05

Applicant: Chung Cheng Wu ,  Shye-Lin Wu

Inventor： Chung Cheng Wu ,  Shye-Lin Wu

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/962

Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape. An anneal procedure results creation of a source/drain region of a first conductivity type in portions of the first SOI fin type shape underlying the first doped insulator layer, and creation of a source/drain region of a second conductivity type in portions of the second SOI fin type shape underlying the second doped insulator layer. Selective deposition of tungsten on exposed top surface of the source/drain regions is then employed to decrease source/drain resistance.

Abstract translation: 已经开发了形成具有N沟道器件和形成在同一SOI层中的P沟道器件的FINFET CMOS器件结构的方法。 该方法特征是形成两个平行的SOI鳍式结构，随后在SOI鳍型结构的侧面上形成栅极绝缘体，并且界定在栅极绝缘体层之间穿过SOI鳍型结构的导电栅极结构。 在第一SOI鳍型形状的暴露的顶表面上形成第一导电类型的掺杂绝缘体层，而在第二SOI鳍型形状的暴露的顶表面上形成第二导电类型的第二掺杂绝缘体层。 退火程序导致在第一掺杂绝缘体层下面的第一SOI鳍型形状的部分中产生第一导电类型的源极/漏极区域，并且在第二导电类型的部分中产生第二导电类型的源极/漏极区域 第二掺杂绝缘体层下方的SOI鳍型。 然后选择性沉积钨在源极/漏极区域的暴露的顶表面上，以降低源极/漏极电阻。