公开(公告)号：US5668035A

公开(公告)日：1997-09-16

申请号：US661259

申请日：1996-06-10

申请人： Chung Hsin Fang ,  Julie Huang ,  Chen-Jong Wang ,  Mong-Song Liang

发明人： Chung Hsin Fang ,  Julie Huang ,  Chen-Jong Wang ,  Mong-Song Liang

IPC分类号： H01L27/105 ,  H01L21/70

CPC分类号： H01L27/105

摘要： A method for fabricating a dual-gate oxide for memory with embedded logic has been achieved. The method is described for forming a thin gate oxide for the peripheral circuits on a DRAM device, while providing a thicker oxide for the memory cells having a boosted word line architecture. The method avoids applying photoresist directly to the gate oxide, and thereby prevents contamination. A first gate oxide is formed on the device areas on the substrate. A first polysilicon layer is deposited and patterned leaving portions over the memory cell areas. The first gate oxide is removed over the peripheral device areas, and is replaced by a thinner second gate oxide. A second polysilicon layer is deposited and patterned to remain over the peripheral device areas. The first and second polysilicon layers, having essentially equal thicknesses, are coated with an insulating layer. The FET gate electrodes for both the peripheral and memory cell areas are simultaneously patterned from the first and second polysilicon layers to complete the DRAM structure up to and including the gate electrodes.

摘要翻译： 已经实现了用于具有嵌入式逻辑的用于存储器的双栅极氧化物的方法。 描述了用于在DRAM器件上形成用于外围电路的薄栅极氧化物的方法，同时为具有升压的字线架构的存储器单元提供较厚的氧化物。 该方法避免了将光致抗蚀剂直接施加到栅极氧化物，从而防止污染。 第一栅极氧化物形成在衬底上的器件区域上。 沉积和图案化的第一多晶硅层将部分留在存储器单元区域上。 第一栅极氧化物在外围器件区域上被去除，并被较薄的第二栅极氧化物代替。 第二多晶硅层被沉积并图案化以保留在外围设备区域上。 具有基本相同厚度的第一和第二多晶硅层被涂覆有绝缘层。 用于外围和存储单元区域的FET栅电极从第一和第二多晶硅层同时构图，以完成直到并包括栅电极的DRAM结构。