公开(公告)号：US09633156B1

公开(公告)日：2017-04-25

申请号：US15047033

申请日：2016-02-18

Applicant: Cirrus Logic, Inc.

Inventor： Bhoodev Kumar ,  Saurabh Singh ,  Lei Zhu

IPC: H03K3/00 ,  G06F17/50

CPC classification number: G06F17/505 ,  G01R31/318541 ,  H03K3/012

Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.

公开(公告)号：US09300275B1

公开(公告)日：2016-03-29

申请号：US14339879

申请日：2014-07-24

Applicant: Cirrus Logic, Inc.

Inventor： Bhoodev Kumar ,  Saurabh Singh ,  Lei Zhu

IPC: H03K3/00 ,  H03K3/012 ,  G06F17/50

CPC classification number: G06F17/505 ,  G01R31/318541 ,  H03K3/012

Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.

Abstract translation: 根据本公开的实施例，用于集成电路设计系统的多位脉冲锁存电路可以包括脉冲发生器和多个锁存器。 脉冲发生器可以被配置为产生脉冲。 多个锁存器可以作为存储元件工作，并且以这样的方式耦合到脉冲发生器，使得多位脉冲锁存电路提供至少两个触发器元件的功能，其中多位脉冲锁存电路可以代替at 通常将由集成电路设计系统使用的至少两个触发器元件。

公开(公告)号：US08664989B1

公开(公告)日：2014-03-04

申请号：US13761237

申请日：2013-02-07

Applicant: Cirrus Logic, Inc.

Inventor： Saurabh Singh ,  Xin Zhao

IPC: H03L7/06

CPC classification number: H03L7/1976

Abstract: The ratio of the output frequency of the PLL to the reference frequency is governed by the ratio of the feedback divider to the output divider. For the case of a fixed-point delta-sigma modulator based PLL, the feedback divide factor can only be a non-recurring/terminating rational number in base-2 (binary) system and the output divide ratio is constrained to be an integer. Hence, the range or resolution of the output frequencies that are possible is inherently limited. To solve this problem, an additional gain factor is introduced in the feedback loop. The gain factor is determined by finding an initial gain factor for which the value of the feedback divide ratio can be represented precisely in the binary format. The closest power of two larger than the initial gain factor is used as the denominator to divide the initial gain factor. The present system and method increases the resolution of such a PLL, while actually saving area/power, by introducing an additional factor within the modulator and also by not affecting the analog part of the circuit.

Abstract translation: PLL的输出频率与参考频率的比值由反馈分频器与输出分频器的比率决定。 对于基于固定点Δ-Σ调制器的PLL的情况，反馈分频因子只能是基2（二进制）系统中的非循环/终止有理数，输出分频比被限制为整数。 因此，可能的输出频率的范围或分辨率固有地受到限制。 为了解决这个问题，在反馈回路中引入了一个额外的增益因子。 增益因子是通过找到能以二进制格式精确地表示反馈分频比的值的初始增益因子来确定的。 使用大于初始增益因子的两个最接近的功率作为分母来分配初始增益因子。 本系统和方法通过在调制器内引入附加因子，并且还不影响电路的模拟部分，增加了这种PLL的分辨率，同时实际上节省了面积/功率。