公开(公告)号：US20230132510A1

公开(公告)日：2023-05-04

申请号：US17980146

申请日：2022-11-03

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John L. MELANSON ,  Lingli ZHANG ,  Paul M. ASTRACHAN ,  James KELTON

IPC: H03M1/06

Abstract: A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator, and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

公开(公告)号：US20230139547A1

公开(公告)日：2023-05-04

申请号：US17980105

申请日：2022-11-03

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Paul M. ASTRACHAN ,  Lingli ZHANG ,  John L. MELANSON ,  James KELTON

IPC: H03M1/06

Abstract: A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

公开(公告)号：US20240291501A1

公开(公告)日：2024-08-29

申请号：US18654911

申请日：2024-05-03

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John L. MELANSON ,  Lingli ZHANG ,  Paul M. ASTRACHAN ,  James KELTON

IPC: H03M1/82 ,  H03M1/18

CPC classification number: H03M1/822 ,  H03M1/183

Abstract: A digital-to-analog converter (DAC) may include an integrator, an input network, and control circuitry. The input network may include a plurality of parallel taps, each having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member is coupled between an input of the digital-to-analog converter and an input of the integrator. The control circuitry may be configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the DAC, such that the control circuitry enables, substantially contemporaneously, an even number of members at a time in order to increase the analog gain, with half of such enabled members in a first group and half of such enabled members in a second group.