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公开(公告)号：US20240429929A1
公开(公告)日：2024-12-26
申请号：US18824537
申请日：2024-09-04
Inventor： John L. MELANSON , Eric J. KING , Thomas H. HOFF , Lingli ZHANG
Abstract: Pulse width modulation (PWM) driver circuitry comprising: a loop filter configured to receive an analog input signal and to output a digital loop filter output signal based on the analog input signal and an analog feedback signal; and a PWM modulator configured to receive a digital signal based on the digital loop filter output signal and to output a PWM signal, wherein the PWM driver circuitry further comprises a feedback path coupled to an output of the PWM driver circuitry for the analog feedback signal.
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公开(公告)号：US20240322817A1
公开(公告)日：2024-09-26
申请号：US18188053
申请日：2023-03-22
Inventor： Ross C. MORGAN , Yongjie CHENG , Lingli ZHANG
IPC: H03K17/687 , H03K17/06
CPC classification number: H03K17/6871 , H03K17/063 , H03K2217/0045
Abstract: This application relates to methods and apparatus for driving a transducer connected between two output nodes in a bridge-tied-load configuration. A driver receives first and second supply voltages and has charge pumps that generate respective first and second boosted voltages. The driver is operable a first driver mode in which each output node is modulated between the first and second supply voltage; a second driver mode in which one output nodes is modulated between the first and second supply voltages and the other output node is modulated between either the first boosted voltage and the first supply voltage or between the second supply voltage and the second boosted voltage; and a third driver mode in which one of the output nodes is modulated between the first supply voltage and the first boosted voltage and the other output node is modulated between the second supply voltage and the second boosted voltage.
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公开(公告)号：US20230344394A1
公开(公告)日：2023-10-26
申请号：US18303750
申请日：2023-04-20
Inventor： John L. MELANSON , Abhishek MUKHERJEE , Lingli ZHANG , Zhaohui HE
CPC classification number: H03F3/2175 , H03F1/3264 , H03F1/0255 , H03F2200/351 , H03F2200/03
Abstract: A system may include an analog loop filter comprising a plurality of analog integrators, the analog loop filter configured to receive an analog signal input and a feedback output signal, at least one sampler for sampling outputs of the analog integrators, a second loop filter coupled between an output of an analog pulse-width modulation driver and a digital pulse-width modulation controller, wherein the second loop filter comprises at least one integrator and is configured to receive sampled outputs of the analog integrators from the at least one sampler and receive a feedback pulse-width modulation signal from the analog pulse-width modulation driver, and a correction subsystem configured to apply a non-linear function to a signal path of the second loop filter in order to compensate for non-linearity introduced as a result of sampling outputs of the analog integrators.
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公开(公告)号：US20180041173A1
公开(公告)日：2018-02-08
申请号：US15661446
申请日：2017-07-27
Inventor： Emmanuel MARCHAIS , Lingli ZHANG , Eric J. KING , Christian LARSEN
CPC classification number: H03F1/32 , H03F3/187 , H03F3/2175 , H03F2200/165 , H03F2200/351
Abstract: In accordance with embodiments of the present disclosure, a system may have a configurable control loop technology, wherein the system comprises a first mode control loop, a second mode control loop and a reconfigurable pulse width modulator (PWM) configured to generate an output signal from an input signal. The reconfigurable PWM may include a digital PWM and an analog PWM and may be configured such that when the first mode control loop is activated, the reconfigurable PWM utilizes the analog PWM to generate the output signal from the input signal and when the second mode control loop is activated, the reconfigurable PWM utilizes the digital PWM to generate the output signal from the input signal and the digital PWM receives its input from a digital proportional integral derivative controller.
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公开(公告)号：US20230139547A1
公开(公告)日：2023-05-04
申请号：US17980105
申请日：2022-11-03
Inventor： Paul M. ASTRACHAN , Lingli ZHANG , John L. MELANSON , James KELTON
IPC: H03M1/06
Abstract: A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.
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Patent Agency Ranking
公开(公告)号：US20230132872A1
公开(公告)日：2023-05-04
申请号：US17898635
申请日：2022-08-30
Inventor： John L. MELANSON , Eric J. KING , Thomas H. HOFF , Lingli ZHANG
IPC: H03M1/06
Abstract: Pulse width modulation (PWM) driver circuitry comprising: a loop filter configured to receive an analog input signal and to output a digital loop filter output signal based on the analog input signal and an analog feedback signal; and a PWM modulator configured to receive a digital signal based on the digital loop filter output signal and to output a PWM signal, wherein the PWM driver circuitry further comprises a feedback path coupled to an output of the PWM driver circuitry for the analog feedback signal.
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公开(公告)号：US20230122394A1
公开(公告)日：2023-04-20
申请号：US17502689
申请日：2021-10-15
Inventor： Ramin ZANBAGHI , Lingli ZHANG , Wei XU , Justin RICHARDSON , John L. MELANSON
Abstract: A system for sensing an electrical quantity may include a sensing stage configured to sense the electrical quantity and generate a sense signal indicative of the electrical quantity, wherein the electrical quantity is indicative of an electrical signal generated by a Class-DG amplifier configured to drive a load wherein the Class-DG amplifier has multiple signal-level common modes and a common-mode compensator configured to compensate for changes to a common-mode voltage of a differential supply voltage of the driver occurring when switching between signal-level common modes of the Class-DG amplifier.
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公开(公告)号：US20240421783A1
公开(公告)日：2024-12-19
申请号：US18820727
申请日：2024-08-30
Inventor： Lingli ZHANG , Theodore M. BURK , Yongjie CHENG , Paul M. ASTRACHAN
Abstract: This application relates to methods and apparatus for driving a transducer. A transducer driver has a switch network is operable to selectively connect a driver output to any of a first set of at least three different switching voltages. which are, in use, maintained throughout a switching cycle of the driver apparatus. The switch network is also operable to selectively connect the driver output to flying capacitor driver. A controller is configured to control the switch network and flying capacitor driver to generate a drive signal at the driver output based on an input signal, wherein in one mode of operation the driver output is switched between two of the first set of switching voltages with a controlled duty cycle and in another mode of operation the driver output is connected to the flying capacitor driver which is switched between first and second states with a controlled duty cycle.
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公开(公告)号：US20240322821A1
公开(公告)日：2024-09-26
申请号：US18188067
申请日：2023-03-22
Inventor： Ross C. MORGAN , Joe WALKER , Yongjie CHENG , Lingli ZHANG
IPC: H03K17/693 , H03K3/017 , H03K17/687
CPC classification number: H03K17/693 , H03K3/017 , H03K17/6871
Abstract: This application relates to methods and apparatus for multichannel drivers for driving transducers in different channels. A multichannel driver has a plurality of output stages configured such that two output nodes can be modulated between selected switching voltages with a controlled duty cycle to generate a differential output signal across a respective transducer, each output stage being operable with different switching voltages in different modes of operation. A first set of two or more of the output stages are arranged to receive a voltage output by a capacitive voltage generator to use as a switching voltage. A controller is configured to control the mode of operation and duty-cycle of each of the output stages based on a respective input signal and also based on operation of the other output stages of the first set.
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公开(公告)号：US20240291501A1
公开(公告)日：2024-08-29
申请号：US18654911
申请日：2024-05-03
Inventor： John L. MELANSON , Lingli ZHANG , Paul M. ASTRACHAN , James KELTON
Abstract: A digital-to-analog converter (DAC) may include an integrator, an input network, and control circuitry. The input network may include a plurality of parallel taps, each having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member is coupled between an input of the digital-to-analog converter and an input of the integrator. The control circuitry may be configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the DAC, such that the control circuitry enables, substantially contemporaneously, an even number of members at a time in order to increase the analog gain, with half of such enabled members in a first group and half of such enabled members in a second group.
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