公开(公告)号：US20250068585A1

公开(公告)日：2025-02-27

申请号：US18235925

申请日：2023-08-21

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Trenton HENRY ,  Sachin DEO ,  Nariankadu HEMKUMAR ,  Younes DJADI ,  Nathan D. P. BUCHANAN

IPC: G06F15/80 ,  G06F9/50 ,  G06F9/54

Abstract: A system may include a plurality of processing cores including at least a first processing core and a second processing core, a shared memory communicatively coupled to and accessible by each of the plurality of processing cores, a global monitor communicatively coupled to each of the plurality of processing cores and configured to control exclusive accesses to memory by each of the plurality of processing cores, and a software architecture embodied in non-transitory computer-readable media and configured to, when read and executed by the multicore processor, partition a plurality of processing tasks between the first processing core and the second processing core.