公开(公告)号：US20240152658A1

公开(公告)日：2024-05-09

申请号：US18500876

申请日：2023-11-02

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Younes DJADI ,  Xingdong DAI ,  Nathan BUCHANAN ,  Nariankadu D. HEMKUMAR

IPC: G06F21/85 ,  G06F11/07 ,  G06F11/14 ,  G06F21/60

CPC classification number: G06F21/85 ,  G06F11/0772 ,  G06F11/1441 ,  G06F21/604

Abstract: A system may include a plurality of processing cores, a target shared among the plurality of processing cores and coupled to the plurality of processing cores via a shared bus, and access control logic configured to, based on access configuration settings associated with the target, control access of requests from each of the plurality of processing cores based on a privilege level of each of the plurality of processing cores, in order to dynamically allocate and re-allocate the target among the plurality of processing cores in accordance with the privilege levels and to dynamically utilize the target in accordance with the privilege levels.

公开(公告)号：US20250068585A1

公开(公告)日：2025-02-27

申请号：US18235925

申请日：2023-08-21

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Trenton HENRY ,  Sachin DEO ,  Nariankadu HEMKUMAR ,  Younes DJADI ,  Nathan D. P. BUCHANAN

IPC: G06F15/80 ,  G06F9/50 ,  G06F9/54

Abstract: A system may include a plurality of processing cores including at least a first processing core and a second processing core, a shared memory communicatively coupled to and accessible by each of the plurality of processing cores, a global monitor communicatively coupled to each of the plurality of processing cores and configured to control exclusive accesses to memory by each of the plurality of processing cores, and a software architecture embodied in non-transitory computer-readable media and configured to, when read and executed by the multicore processor, partition a plurality of processing tasks between the first processing core and the second processing core.

公开(公告)号：US20210029319A1

公开(公告)日：2021-01-28

申请号：US16522580

申请日：2019-07-25

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： James P. MCFARLAND ,  Nariankadu D. HEMKUMAR ,  Sachin DEO ,  Younes DJADI

IPC: H04N5/378 ,  H04N5/374 ,  H04N5/3745 ,  H04N19/146 ,  H04N19/184 ,  H04N19/132

Abstract: A system may include a processing engine and an analog-to-digital conversion interface subsystem communicatively coupled to the processing engine. The processing engine may be configured to process feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate and based on processing of the feedback data, generate digital control signals for controlling a system under control. The analog-to-digital conversion interface subsystem may be configured to flexibly control the processing of the processing engine and the generation of digital control signals by the processing engine to minimize latency in the generation of the digital control signals due to processing of the processing engine.