公开(公告)号：US20210029319A1

公开(公告)日：2021-01-28

申请号：US16522580

申请日：2019-07-25

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： James P. MCFARLAND ,  Nariankadu D. HEMKUMAR ,  Sachin DEO ,  Younes DJADI

IPC: H04N5/378 ,  H04N5/374 ,  H04N5/3745 ,  H04N19/146 ,  H04N19/184 ,  H04N19/132

Abstract: A system may include a processing engine and an analog-to-digital conversion interface subsystem communicatively coupled to the processing engine. The processing engine may be configured to process feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate and based on processing of the feedback data, generate digital control signals for controlling a system under control. The analog-to-digital conversion interface subsystem may be configured to flexibly control the processing of the processing engine and the generation of digital control signals by the processing engine to minimize latency in the generation of the digital control signals due to processing of the processing engine.

公开(公告)号：US20250093922A1

公开(公告)日：2025-03-20

申请号：US18469101

申请日：2023-09-18

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Sachin DEO ,  Nariankadu HEMKUMAR ,  Mark MAY ,  Akhilesh PERSHA ,  Eric B. SMITH ,  Donelson A. SHANNON

IPC: G06F1/26

Abstract: A system may include a first controller and a second controller communicatively coupled to the first controller via a bidirectional communication channel and configured to drive a load in accordance with a target current signal, sample a load voltage of the load at a sample rate substantially slower than a time duration of electrical transients of the load, calculate a resistance of the load based on a current signal and the load voltage and communicate information indicative of the resistance to the first controller at a time interval substantially slower than the time duration of electrical transients of the load, detect when one or more accuracy-reducing events associated with the system occur, wherein an accuracy-reducing event is one which negatively affects accuracy of calculation of the resistance, and modify the information provided to the first controller when one or more accuracy-reducing events occur.

公开(公告)号：US20250068585A1

公开(公告)日：2025-02-27

申请号：US18235925

申请日：2023-08-21

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Trenton HENRY ,  Sachin DEO ,  Nariankadu HEMKUMAR ,  Younes DJADI ,  Nathan D. P. BUCHANAN

IPC: G06F15/80 ,  G06F9/50 ,  G06F9/54

Abstract: A system may include a plurality of processing cores including at least a first processing core and a second processing core, a shared memory communicatively coupled to and accessible by each of the plurality of processing cores, a global monitor communicatively coupled to each of the plurality of processing cores and configured to control exclusive accesses to memory by each of the plurality of processing cores, and a software architecture embodied in non-transitory computer-readable media and configured to, when read and executed by the multicore processor, partition a plurality of processing tasks between the first processing core and the second processing core.