公开(公告)号：US20240243701A1

公开(公告)日：2024-07-18

申请号：US18098264

申请日：2023-01-18

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Neel PRAMANIK ,  Prashanth DRAKSHAPALLI

IPC: H03F1/12

CPC classification number: H03F1/12 ,  H03F2200/153

Abstract: An amplifier circuit may include a first gain stage configured to receive an input signal at the first gain stage input and apply a first gain to the input signal to generate a first gain stage output signal at the first gain stage output, a second gain stage configured to receive the first gain stage output signal at the second gain stage input and apply a second gain to the first gain stage output signal to generate a second gain stage output signal at the second gain stage output, a feedforward gain stage configured to receive the input signal at the feedforward gain stage input and apply a feedforward gain to the input signal to generate a feedforward gain stage output signal at the feedforward gain stage output, and a compensation network coupled between the first gain stage output and the feedforward gain stage output.

公开(公告)号：US20230122151A1

公开(公告)日：2023-04-20

申请号：US17848550

申请日：2022-06-24

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Zhaohui HE ,  Neel PRAMANIK ,  Lingli ZHANG ,  Wei XU ,  Prashanth DRAKSHAPALLI

IPC: H03F3/45

Abstract: A method for calibrating a fully-differential input system may include determining a first voltage of a first node of the fully-differential input system, wherein the first node is coupled at the first node to a plurality of first resistors in a first star configuration, determining a second voltage of a second node of the fully-differential input system, wherein the second node is coupled at the second node to a plurality of second resistors in a second star configuration, each resistor of the plurality of second resistors corresponding to a respective resistor of the plurality of first resistors, and trimming individual resistances of the plurality of first resistors and the plurality of second resistors in order to maintain a difference of a first voltage at the first node and a second voltage of the second node at approximately zero.