公开(公告)号：US20190198397A1

公开(公告)日：2019-06-27

申请号：US16221939

申请日：2018-12-17

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Francois ANDRIEU ,  Lamine Benaissa ,  Laurent Brunet

IPC分类号： H01L21/822 ,  H01L21/768 ,  H01L27/06 ,  H01L27/12

CPC分类号： H01L21/8221 ,  H01L21/2007 ,  H01L21/76801 ,  H01L21/76879 ,  H01L21/7688 ,  H01L21/823437 ,  H01L21/823842 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1203

摘要： Fabrication of a circuit with superposed transistors, comprising assembly of a structure comprising transistors formed from a first semiconducting layer with a support (100) provided with a second semiconducting layer (102) in which transistors are provided on a higher level (N2), the second semiconducting layer (102) being coated with a thin layer (101) of silicon oxide, the assembly of said structure and the support (100) being made by direct bonding in which the thin silicon oxide layer (101) is bonded to oxidised portions (37b, 37c) of getter material.

公开(公告)号：US10319628B2

公开(公告)日：2019-06-11

申请号：US15715619

申请日：2017-09-26

申请人： Commissariat a l'energie atomique et aux energies alternatives

发明人： Fabien Deprat ,  Perrine Batude ,  Laurent Brunet ,  Claire Fenouillet-Beranger ,  Maud Vinet

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L21/3213

摘要： A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.

公开(公告)号：US11024544B2

公开(公告)日：2021-06-01

申请号：US16221939

申请日：2018-12-17

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Francois Andrieu ,  Lamine Benaissa ,  Laurent Brunet

IPC分类号： H01L21/00 ,  H01L21/822 ,  H01L21/768 ,  H01L27/12 ,  H01L27/06 ,  H01L21/20 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234

摘要： Fabrication of a circuit with superposed transistors includes assembly of a structure having transistors formed from a first semiconducting layer with a support provided with a second semiconducting layer in which transistors are provided on a higher level. The second semiconducting layer is coated with a thin layer of silicon oxide. The assembly of said structure and the support is made by direct bonding in which the thin silicon oxide layer is bonded to oxidised portions of getter material.