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公开(公告)号:US20080310532A1
公开(公告)日:2008-12-18
申请号:US12097773
申请日:2006-12-14
申请人: Constant Paul Marie Jozef Baggen , Alessio Filippi , Sri Andari Husen , Maurice Leonardus Anna Stassen , Volker Aue , Andreas Bury , Thomas Fliess , Yann Casamajou , Frederic Pirot
发明人: Constant Paul Marie Jozef Baggen , Alessio Filippi , Sri Andari Husen , Maurice Leonardus Anna Stassen , Volker Aue , Andreas Bury , Thomas Fliess , Yann Casamajou , Frederic Pirot
IPC分类号: H04L27/28
CPC分类号: H04L27/261
摘要: In an OFDM mobile communications system, an algorithm for forming a preliminary estimate of the channel on pilot subcarriers is carried out. Based on this preliminary estimate, a channel property is estimated. This channel property is then used to decide whether to enter a mobile receiver mode or a stationary receiver mode. For example, in the mobile mode channel estimation is performed using only pilot symbols from the current symbol period, while in the static mode channel estimation is performed using pilot symbols from the current symbol period and pilot symbols from other symbol periods.
摘要翻译: 在OFDM移动通信系统中,执行用于形成导频子载波上的信道的初步估计的算法。 根据这个初步估计,估计一个频道属性。 然后,该频道属性用于决定是否进入移动接收机模式或静态接收机模式。 例如,在移动模式中,仅使用来自当前符号周期的导频符号进行信道估计,而在静态模式中,使用来自当前符号周期的导频符号和来自其他符号周期的导频符号来执行信道估计。
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2.
公开(公告)号:US08744374B2
公开(公告)日:2014-06-03
申请号:US12963683
申请日:2010-12-09
申请人: Volker Aue , Thomas Fliess
发明人: Volker Aue , Thomas Fliess
IPC分类号: H04B7/02
CPC分类号: H04W52/146 , H04B7/0404 , H04B7/0413 , H04B7/0671 , H04B7/0682
摘要: Methods and apparatus for uplink data transmission in a Long Term Evolution (LTE) compliant communication system use beam-forming in the uplink to increase the range of LTE compliant wireless communication terminals. Methods are provided for steering the beam in an optimal direction towards the base station, both for time division duplex (TDD) and frequency division duplex (FDD) communication schemes.
摘要翻译: 在长期演进(LTE)兼容通信系统中用于上行链路数据传输的方法和装置在上行链路中使用波束形成来增加LTE兼容的无线通信终端的范围。 提供了用于在朝向基站的最佳方向上将时间分割双工(TDD)和频分双工(FDD)通信方案进行操纵的方法。
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公开(公告)号:US08572299B2
公开(公告)日:2013-10-29
申请号:US13251323
申请日:2011-10-03
申请人: Uwe Pross , Tobias Weber , Gunnar Nitsche , Thomas Fliess
发明人: Uwe Pross , Tobias Weber , Gunnar Nitsche , Thomas Fliess
CPC分类号: G06F9/3881
摘要: A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.
摘要翻译: 硬件加速器模块由系统处理器经由系统总线驱动,以便根据由处理器定义的参数集来顺序地处理数据流的数据块。 模块包括适于从系统处理器接收参数集的寄存器块,适于接收流数据的加速器核心,以由参数集定义的方式处理所述流数据的数据块,以及输出处理后的流数据,以及 参数缓冲块,其适于连续地存储多个参数集,并且作为硬件加速器核心的忙状态的函数,将参数集顺序地提供给硬件加速器核心。 参数缓冲块可以减少硬件加速器的停机时间,增加数据吞吐量,并降低驱动多个硬件加速器的处理器中处理器过载的风险。
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