公开(公告)号：US20090152591A1

公开(公告)日：2009-06-18

申请号：US11957626

申请日：2007-12-17

申请人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： H01L27/10

CPC分类号： G06F17/5036

摘要： A design structure for a circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes and input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.

摘要翻译： 用于选择性地将集成电路连接到集成电路外部的元件的电路的设计结构。 该电路包括输入/​​输出元件，其根据功率需求或集成电路的信号带宽需求选择性地连接输入/输出引脚。 输入/输出元件包括将输入/输出引脚连接到诸如电源或外部信号路径的外部元件的一个或多个开关器件。 输入/输出元件还包括将输入/输出引脚连接到诸如电力网络或内部信号线的内部元件的一个或多个开关器件。

公开(公告)号：US07949978B2

公开(公告)日：2011-05-24

申请号：US11934804

申请日：2007-11-05

申请人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： G06F17/50 ,  H03K19/003

CPC分类号： G06F17/505

摘要： A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-chip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributors; the noise event arbiter determining when each noise contributor may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributor as to when permission is granted to execute its operations.

摘要翻译： 一种设计结构集成电路（IC）系统架构，其允许通过提供一种方法来减少片上或跨芯片的瞬态噪声预算，以避免来自至少两个功能逻辑块（即噪声贡献者）的同时高电流需求事件， 被披露。 IC系统架构的实施例包括至少一个噪声事件仲裁器和至少两个噪声贡献器块。 调度片上噪声事件以避免同时有效的瞬态噪声事件的方法可以包括但不限于：噪声事件仲裁器同时从多个噪声贡献者接收多个请求操作的请求; 噪声事件仲裁者确定每个噪声贡献者何时可以基于预先建立的dI / dt预算执行操作; 噪声事件仲裁器通知每个噪声贡献者关于何时授权执行其操作。

公开(公告)号：US08122165B2

公开(公告)日：2012-02-21

申请号：US11954600

申请日：2007-12-12

申请人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： G06F3/00 ,  G06F13/40

CPC分类号： G06F1/26 ,  Y10T307/911

摘要： A circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes an input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.

摘要翻译： 将集成电路选择性地连接到集成电路外部的元件的电路。 该电路包括根据功率需求或集成电路的信号带宽需求选择性地连接输入/输出引脚的输入/输出元件。 输入/输出元件包括将输入/输出引脚连接到诸如电源或外部信号路径的外部元件的一个或多个开关器件。 输入/输出元件还包括将输入/输出引脚连接到诸如电力网络或内部信号线的内部元件的一个或多个开关器件。

公开(公告)号：US20090152594A1

公开(公告)日：2009-06-18

申请号：US11954600

申请日：2007-12-12

申请人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： H01L27/10

CPC分类号： G06F1/26 ,  Y10T307/911

摘要： A circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes an input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.

摘要翻译： 将集成电路选择性地连接到集成电路外部的元件的电路。 该电路包括根据功率需求或集成电路的信号带宽需求选择性地连接输入/输出引脚的输入/输出元件。 输入/输出元件包括将输入/输出引脚连接到诸如电源或外部信号路径的外部元件的一个或多个开关器件。 输入/输出元件还包括将输入/输出引脚连接到诸如电力网络或内部信号线的内部元件的一个或多个开关器件。

公开(公告)号：US08020137B2

公开(公告)日：2011-09-13

申请号：US11957626

申请日：2007-12-17

申请人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A design structure for a circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes and input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.

摘要翻译： 用于选择性地将集成电路连接到集成电路外部的元件的电路的设计结构。 该电路包括输入/​​输出元件，其根据功率需求或集成电路的信号带宽需求选择性地连接输入/输出引脚。 输入/输出元件包括将输入/输出引脚连接到诸如电源或外部信号路径的外部元件的一个或多个开关器件。 输入/输出元件还包括将输入/输出引脚连接到诸如电力网络或内部信号线的内部元件的一个或多个开关器件。

公开(公告)号：US07545165B2

公开(公告)日：2009-06-09

申请号：US11621175

申请日：2007-01-09

申请人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： H03K19/003

CPC分类号： H03K19/0005

摘要： Integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC systems architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-clip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributers; the noise event arbiter determining when each noise contributer may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributer as to when permission is granted to execute its operations.

摘要翻译： 集成电路（IC）系统架构允许通过提供避免来自至少两个功能逻辑块（即噪声贡献者）的同时高电流需求事件的手段来减少片上或跨芯片的瞬态噪声预算。 IC系统架构的实施例包括至少一个噪声事件仲裁器和至少两个噪声贡献器块。 调度片上噪声事件以避免同时的主动瞬态噪声事件的方法可以包括但不限于：噪声事件仲裁器同时从多个噪声贡献者同时接收多个请求操作; 噪声事件仲裁器确定每个噪声分配器何时可以基于预先建立的dI / dt预算来执行操作; 并且噪声事件仲裁器通知每个噪声贡献者关于何时授权执行其操作。

公开(公告)号：US20090119625A1

公开(公告)日：2009-05-07

申请号：US11934804

申请日：2007-11-05

申请人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-chip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributors; the noise event arbiter determining when each noise contributor may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributor as to when permission is granted to execute its operations.

摘要翻译： 一种设计结构集成电路（IC）系统架构，其允许通过提供一种方法来减少片上或跨芯片的瞬态噪声预算，以避免来自至少两个功能逻辑块（即噪声贡献者）的同时高电流需求事件， 被披露。 IC系统架构的实施例包括至少一个噪声事件仲裁器和至少两个噪声贡献器块。 调度片上噪声事件以避免同时有效的瞬态噪声事件的方法可以包括但不限于：噪声事件仲裁器同时从多个噪声贡献者接收多个请求操作的请求; 噪声事件仲裁者确定每个噪声贡献者何时可以基于预先建立的dI / dt预算执行操作; 噪声事件仲裁器通知每个噪声贡献者关于何时授权执行其操作。

公开(公告)号：US20080164903A1

公开(公告)日：2008-07-10

申请号：US11621175

申请日：2007-01-09

申请人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： H03K17/16

CPC分类号： H03K19/0005

摘要： Integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC systems architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-clip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributers; the noise event arbiter determining when each noise contributer may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributer as to when permission is granted to execute its operations.

摘要翻译： 集成电路（IC）系统架构允许通过提供避免来自至少两个功能逻辑块（即噪声贡献者）的同时高电流需求事件的手段来减少片上或跨芯片的瞬态噪声预算。 IC系统架构的实施例包括至少一个噪声事件仲裁器和至少两个噪声贡献器块。 调度片上噪声事件以避免同时的主动瞬态噪声事件的方法可以包括但不限于：噪声事件仲裁器同时从多个噪声贡献者同时接收多个请求操作; 噪声事件仲裁器确定每个噪声分配器何时可以基于预先建立的dI / dt预算来执行操作; 并且噪声事件仲裁器通知每个噪声贡献者关于何时授权执行其操作。

公开(公告)号：US07849426B2

公开(公告)日：2010-12-07

申请号：US11931144

申请日：2007-10-31

申请人： Kenneth J. Goodnow ,  Douglas W. Kemerer ,  Stephen G. Shuma ,  Oscar C. Strohacker ,  Mark S. Styduhar ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Kenneth J. Goodnow ,  Douglas W. Kemerer ,  Stephen G. Shuma ,  Oscar C. Strohacker ,  Mark S. Styduhar ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： G06F17/50 ,  G01R31/26

CPC分类号： G06F17/5063

摘要： The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.

摘要翻译： 本发明的实施例提供了用于检测和补偿负偏压温度不稳定性（NBTI）诱导的阈值劣化的设计结构。 提供一种半导体器件，其包括至少一个应力器件，其具有施加到其栅极节点的电压和至少一个具有零栅极至源极电压的参考器件。 还提供控制器来配置设备和/或参考设备的节点电压以反映在数字和模拟电路应用中发现的设备操作的不同区域。 此外，控制器测量应力装置和参考装置之间的电流差，以确定在应力装置中是否发生了NBTI诱导的阈值劣化。 控制器还调整应力装置的输出电源电压，直到应力装置的性能与参考装置的性能匹配以解决NBTI诱发的阈值劣化。

公开(公告)号：US08010813B2

公开(公告)日：2011-08-30

申请号：US12051001

申请日：2008-03-19

申请人： Kenneth J. Goodnow ,  Stephen G. Shuma ,  Oscar C. Strohacker ,  Mark S. Styduhar ,  Peter A. Twombly ,  Andrew S. Wienick ,  Paul S. Zuchowski

发明人： Kenneth J. Goodnow ,  Stephen G. Shuma ,  Oscar C. Strohacker ,  Mark S. Styduhar ,  Peter A. Twombly ,  Andrew S. Wienick ,  Paul S. Zuchowski

IPC分类号： G06F1/00 ,  G06F11/00

CPC分类号： H03K19/00392

摘要： Disclosed is a design structure for an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.

摘要翻译： 公开了一种用于相关联的第一系统的设计结构，用于在存在导致在系统设备内展现性能下降和恢复性能的现象的情况下延长第二系统的产品寿命。 第一系统包括并入第二系统中的重复设备（例如，在共享总线上）。 这些重复设备适于在该第二系统内独立地执行相同的功能。 参考信号发生器，参考信号比较器，功率控制器和状态机组合起来可以适应于基于性能下降的测量来在复制设备之间的第二系统内的相同功能的无缝切换性能，以允许 设备恢复。 状态机可访问的预定策略指示何时以及是否启动切换。