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公开(公告)号：US5860096A
公开(公告)日：1999-01-12
申请号：US768417
申请日：1996-12-18
CPC分类号： G06F9/3814 , G06F12/0897 , G06F9/3802
摘要： A multi-level instruction cache memory system for a computer processor. A relatively large cache has both instructions and data. The large cache is the primary source of data for the processor. A smaller cache dedicated to instructions is also provided. The smaller cache is the primary source of instructions for the processor. Instructions are copied from the larger cache to the smaller cache during times when the processor is not accessing data in the larger cache. A prefetch buffer transfers instructions from the larger cache to the smaller cache. If a cache miss occurs for the smaller cache, and the instruction is in the prefetch buffer, the system provides the instruction with no delay relative to a fetch from the smaller instruction cache. If a cache miss occurs for the smaller cache, and the instruction is being fetched from the larger cache, or available in the larger cache, the system provides the instruction with minimal delay relative to a fetch from the smaller instruction cache.
摘要翻译： 一种用于计算机处理器的多级指令高速缓冲存储器系统。 相对较大的缓存具有指令和数据。 大型缓存是处理器的主要数据源。 还提供了一个专用于指令的较小缓存。 较小的缓存是处理器的主要指令源。 在处理器未访问较大缓存中的数据的时间期间，指令将从更大的缓存复制到较小的缓存。 预取缓冲区将指令从较大的缓存传输到较小的缓存。 如果较小的缓存出现高速缓存未命中，并且该指令位于预取缓冲区中，则该系统相对于从较小的指令高速缓存提取的指令没有延迟。 如果较小的缓存出现高速缓存未命中，并且指令正在从较大的缓存中取出，或者在较大的缓存中可用，则该系统相对于从较小的指令高速缓存取出的延迟最小化。
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公开(公告)号：US07343479B2
公开(公告)日：2008-03-11
申请号：US10602916
申请日：2003-06-25
申请人： Patrick Knebel , Kevin David Safford , Donald Charles Soltis, Jr. , Joel D Lamb , Stephen R. Undy , Russell C Brockmann
发明人： Patrick Knebel , Kevin David Safford , Donald Charles Soltis, Jr. , Joel D Lamb , Stephen R. Undy , Russell C Brockmann
IPC分类号： G06F9/455
CPC分类号： G06F9/30174 , G06F9/30167 , G06F9/382 , G06F9/3853
摘要： The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexer or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.
摘要翻译： 本发明是用于在单个芯片上实现两个架构的方法。 该方法使用提取引擎来检索指令。 如果指令是宏指令，则将宏指令解码为微指令，然后在仿真引擎内使用捆绑器捆绑这些微指令。 捆绑包并行发布并分发到执行引擎并包含预解码位，以便执行引擎将它们视为微指令。 在被传送到执行引擎之前，可以将指令保存在缓冲器中。 该方法还可以通过使用多路复用器或其他方式，从模拟引擎的捆绑微指令和直接从获取引擎进行的本机微指令之间进行选择。 本地微指令和捆绑的微指令都可以保存在缓冲区中。 该方法还向执行引擎发送附加信息。
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3.发明授权Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information 失效用于使用包含微指令和模板信息的束来在芯片中实现两个架构的方法和装置公开(公告)号：US06618801B1
公开(公告)日：2003-09-09
申请号：US09496845
申请日：2000-02-02
申请人： Patrick Knebel , Kevin David Safford , Donald Charles Soltis, Jr. , Joel D Lamb , Stephen R. Undy , Russell C Brockmann
发明人： Patrick Knebel , Kevin David Safford , Donald Charles Soltis, Jr. , Joel D Lamb , Stephen R. Undy , Russell C Brockmann
IPC分类号： G06F1500
CPC分类号： G06F9/30174 , G06F9/30167 , G06F9/382 , G06F9/3853
摘要： The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexor or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.
摘要翻译： 本发明是用于在单个芯片上实现两个架构的方法。 该方法使用提取引擎来检索指令。 如果指令是宏指令，则将宏指令解码为微指令，然后在仿真引擎内使用捆绑器捆绑这些微指令。 捆绑包并行发布并分发到执行引擎并包含预解码位，以便执行引擎将它们视为微指令。 在被传送到执行引擎之前，可以将指令保存在缓冲器中。 该方法还可以选择来自仿真引擎的捆绑微指令和直接来自取指引擎的本机微指令，通过使用多路复用器或其他方式。 本地微指令和捆绑的微指令都可以保存在缓冲区中。 该方法还向执行引擎发送附加信息。
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4.发明授权Simultaneous execution of two memory reference instructions with only one address calculation 失效同时执行两个存储器参考指令，只需一次地址计算
公开(公告)号：US5829049A
公开(公告)日：1998-10-27
申请号：US785105
申请日：1997-01-21
CPC分类号： G06F9/30043 , G06F9/3853
摘要： A method of improving the performance of a computer processor by recognizing that two consecutive register instructions can be executed simultaneously and executing the two instructions simultaneously while generating a single data address and while performing exception checking on a single data address. During an instruction fetch process, two consecutive instructions are tested to determine if both are either register load instructions or register save instructions. If both instructions are load or save register instructions, the corresponding data addresses are tested to see if both data addresses are in the same double word. If both data addresses are in the same double word, then the instructions are executed simultaneously. Only one data address generation is required and exception processing is performed on only one data address. In one example embodiment, a simplified test rapidly ensures that both data addresses are in the same double word, but also requires the base addresses to be at an even word boundary. In a second embodiment, where the processor includes an alignment test as a separate test, an even more simple test rapidly ensures that both data address are in the same double word without checking alignment.
摘要翻译： 通过识别同时执行两个连续的寄存器指令并且同时执行两个指令同时生成单个数据地址并且同时对单个数据地址执行异常检查来改善计算机处理器的性能的方法。 在指令提取过程中，测试两个连续的指令，以确定两者是寄存器加载指令还是寄存器保存指令。 如果两个指令都是加载或保存寄存器指令，则对相应的数据地址进行测试，以查看两个数据地址是否都在相同的双字中。 如果两个数据地址都是相同的双字，则同时执行指令。 只需要一个数据地址生成，并且只对一个数据地址执行异常处理。 在一个示例实施例中，简化测试快速确保两个数据地址都在相同的双字中，但也要求基地址处于偶数字边界。 在第二实施例中，其中处理器包括作为单独测试的对准测试，甚至更简单的测试快速确保两个数据地址都在相同的双字中，而不检查对齐。
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公开(公告)号：US08505020B2
公开(公告)日：2013-08-06
申请号：US12870835
申请日：2010-08-29
IPC分类号： G06F9/46 , G06F15/173 , G06F1/00 , G06F11/00
CPC分类号： G06F9/5088
摘要： An event calling for a migration of a workload from a source processor set of processing units to a target processor set of processing units is detected. Processes of the workload are allocated to a second processor set of processing units so that some workload processes are executed on the source processor set and some workload processes are executed on a second processor set of processor units. Then, some workload processes are allocated to the second processor set so that no workload process is executing on the source processor set and at least some of said processes are executing on the second process set. The second processor set can be the target processor set or an intermediate processor set from which the workload is migrated to the target processor set.
摘要翻译： 检测到要求将工作负载从源处理器集合处理单元迁移到处理单元集合的事件。 工作负载的处理被分配给处理单元的第二处理器集合，使得在源处理器集上执行一些工作负载过程，并且在第二处理器单元集合上执行一些工作负载过程。 然后，一些工作负载过程被分配给第二处理器集，使得在源处理器集上不执行工作负载过程，并且至少一些所述进程在第二进程集上执行。 第二处理器集合可以是目标处理器集合或中间处理器集合，工作负载从该集中迁移到目标处理器集合。
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公开(公告)号：US20080104329A1
公开(公告)日：2008-05-01
申请号：US11554827
申请日：2006-10-31
申请人： Blaine D. Gaither , Patrick Knebel
发明人： Blaine D. Gaither , Patrick Knebel
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0804 , G06F12/0815 , G06F12/0897
摘要： A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.
摘要翻译： 提供了用于将处理器与主存储器可操作地耦合的高速缓存。 高速缓存包括与高速缓冲存储器可操作地耦合的高速缓冲存储器和高速缓存控制器。 缓存控制器被配置为接收由高速缓冲存储器或主存储器满足的存储器请求。 此外，高速缓存控制器被配置为处理高速缓存活动信息以使至少一个存储器请求绕过高速缓冲存储器。
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7.发明授权Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions 失效用于在用微指令进行仿真时，在生成和消耗宏指令之间有效地生成，存储和消耗算术标记的方法和装置公开(公告)号：US06807625B1
公开(公告)日：2004-10-19
申请号：US09507032
申请日：2000-02-18
申请人： Patrick Knebel , Mark Gibson , Rohit Bhatia , Kevin David Safford
发明人： Patrick Knebel , Mark Gibson , Rohit Bhatia , Kevin David Safford
IPC分类号： G06F1500
CPC分类号： G06F9/30014 , G06F9/30018 , G06F9/30094 , G06F9/3842
摘要： An apparatus and method for efficiently generating arithmetic flags in a computer system. The system includes an eflags register to stored partially computed flags computed by an arithmetic logic unit. The stored partial flags are computed in one cycle. The stored flags are decoded by one of two consuming instructions, PRODF or TBIT, in a second cycle.
摘要翻译： 一种用于在计算机系统中有效地产生算术标志的装置和方法。 该系统包括用于存储由算术逻辑单元计算的部分计算的标志的eflags寄存器。 存储的部分标志在一个周期内计算。 存储的标志在第二个周期中由两个消耗指令PRODF或TBIT中的一个解码。
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公开(公告)号：US08683139B2
公开(公告)日：2014-03-25
申请号：US11554827
申请日：2006-10-31
申请人： Blaine D. Gaither , Patrick Knebel
发明人： Blaine D. Gaither , Patrick Knebel
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0804 , G06F12/0815 , G06F12/0897
摘要： A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.
摘要翻译： 提供了用于将处理器与主存储器可操作地耦合的高速缓存。 高速缓存包括与高速缓冲存储器可操作地耦合的高速缓冲存储器和高速缓存控制器。 缓存控制器被配置为接收由高速缓冲存储器或主存储器满足的存储器请求。 此外，高速缓存控制器被配置为处理高速缓存活动信息以使至少一个存储器请求绕过高速缓冲存储器。
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9.发明授权Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit 有权用于验证中央处理器单元的行为模型的细粒度正确性的方法和装置公开(公告)号：US06625759B1
公开(公告)日：2003-09-23
申请号：US09502366
申请日：2000-02-18
申请人： Jeremy Petsinger , Kevin David Safford , Karl P. Brummel , Russell C. Brockmann , Bruce A. Long , Patrick Knebel
发明人： Jeremy Petsinger , Kevin David Safford , Karl P. Brummel , Russell C. Brockmann , Bruce A. Long , Patrick Knebel
IPC分类号： H02H305
CPC分类号： G06F11/261
摘要： A method and an apparatus checks the fine-grain correctness of a microcode machine central processor unit (CPU) behavioral model. Macroinstructions are decomposed into microinstructions and each microinstruction is executed sequentially. A sequence of microinstructions is determined by an emulated microinstruction sequencer, using dynamic execution information, including information from execution of prior microinstructions in the sequence of microinstructions. At the end of execution of each microinstruction, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted. After execution of all microinstructions in the microinstruction sequence, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted.
摘要翻译： 一种方法和装置检查微码机中央处理器单元（CPU）行为模型的细粒度正确性。 宏指令被分解为微指令，并且每个微指令都被顺序执行。 微指令序列由模拟的微指令测序仪确定，使用动态执行信息，包括在微指令序列中执行先前微指令的信息。 在每个微指令的执行结束时，将参考状态与行为模型的相应状态进行比较，并且注意到任何差异。 在微指令序列中执行所有微指令之后，将参考状态与行为模型的相应状态进行比较，并记录任何差异。
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10.发明授权Circuitry for providing external access to signals that are internal to an integrated circuit chip package 失效用于提供对集成电路芯片封装内部信号的外部访问的电路
公开(公告)号：US6003107A
公开(公告)日：1999-12-14
申请号：US707936
申请日：1996-09-10
CPC分类号： G06F7/02
摘要： Circuitry for providing external access to signals that are internal to an integrated circuit chip package. A plurality of N:1 multiplexers are physically distributed throughout the integrated circuit die. Each of the multiplexers has its N inputs coupled to a nearby set of N nodes within the integrated circuit, and each of the multiplexers is coupled to a source of select information operable to select one node from the set of N nodes for external access. Each of the multiplexers has its output coupled to an externally-accessible chip pad. The integrated circuit is a microprocessor, and the source of select information may include a storage element. If so, additional circuitry is provided for writing data from a register of the microprocessor to the storage element using one or more microprocessor instructions. Each multiplexer may be coupled to a different source of select information, or all multiplexers may be coupled to the same select information. Moreover, a fixed set of interconnect traces may be provided to couple a fixed set of nodes to an additional set of externally-accessible chip pads. One or more M:1 multiplexers may also be provided, having their M inputs coupled to M different outputs of the N:1 multiplexers. Each of the M:1 multiplexers may be coupled to a second source of select information. Preferably, the outputs of the M:1 multiplexers will be coupled to a circuitry for facilitating debug and performance monitoring of the integrated circuit.
摘要翻译： 用于提供对集成电路芯片封装内部信号的外部访问的电路。 多个N：1复用器物理地分布在整个集成电路管芯中。 每个复用器具有其N个输入耦合到集成电路内的附近的一组N个节点，并且每个多路复用器耦合到可选择信息的源，用于从用于外部访问的N个节点的集合中选择一个节点。 每个多路复用器的输出耦合到外部可访问的芯片焊盘。 集成电路是微处理器，选择信息的源可以包括存储元件。 如果是这样，则提供附加电路用于使用一个或多个微处理器指令将数据从微处理器的寄存器写入存储元件。 每个复用器可以耦合到不同的选择信息源，或者所有复用器可以耦合到相同的选择信息。 此外，可以提供固定的一组互连轨迹以将固定的一组节点耦合到另外一组外部可访问的芯片焊盘。 还可以提供一个或多个M：1多路复用器，其M个输入端耦合到N：1多路复用器的M个不同输出。 M：1多路复用器中的每一个可以耦合到第二选择信息源。 优选地，M：1多路复用器的输出将耦合到用于促进集成电路的调试和性能监视的电路。
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