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1.发明授权Low latency message processor interface using memory mapped Read/Write Windows 失效低延迟消息处理器接口使用内存映射读/写Windows
公开(公告)号：US5696936A
公开(公告)日：1997-12-09
申请号：US428054
申请日：1995-04-25
IPC分类号： G06F12/08
CPC分类号： G06F12/0879 , G06F12/0897
摘要： A low latency software and hardware interface between a microprocessor and Network Interface Unit is disclosed. The Network Interface Unit interfaces to the microprocessor's Level 2 cache interface, which provides burst transfers of cache lines between the microprocessor and Network Interface Unit. The Network Interface Unit is memory mapped into the microprocessor's address space. Two memory mapped cache lines are used to write commands to the Network Interface Unit's Write Window and another two cache lines are used to read results of the commands from the Network Interface Unit's Read Window. The Write Window is a three port register file. Data is written into one write port and read simultaneously from two read ports. One read port is used during read operations to the Write Window while the other is used during command execution to move data to the Internal Structures block. The Read Window is a 2-1 multiplexor that is 128 bits wide. On a read operation data may be selected from the Write Window or the Internal Structures.
摘要翻译： 公开了微处理器和网络接口单元之间的低延迟软件和硬件接口。 网络接口单元连接到微处理器的2级缓存接口，该接口在微处理器和网络接口单元之间提供高速缓存线的突发传输。 网络接口单元被存储器映射到微处理器的地址空间。 两个内存映射缓存行用于将命令写入网络接口单元的写入窗口，另外两条缓存行用于从网络接口单元的“读取窗口”读取命令的结果。 写入窗口是一个三端口寄存器文件。 将数据写入一个写入端口，并从两个读取端口同时读取。 在写入窗口的读取操作期间使用一个读取端口，而在命令执行期间使用另一个读取端口将数据移动到“内部结构”块。 读窗口是128位宽的2-1多路复用器。 在读取操作数据可以从写入窗口或内部结构中选择。
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2.发明授权Methods and apparatus for exchanging active messages in a parallel processing computer system 失效在并行处理计算机系统中交换活动消息的方法和装置
公开(公告)号：US5710923A
公开(公告)日：1998-01-20
申请号：US428684
申请日：1995-04-25
CPC分类号： G06F9/546
摘要： A method for communicating active messages among nodes of a parallel processing computer system is disclosed. The active messages are defined by .mu.threads, and the method comprises the steps of: (a) generating a .mu.thread comprising an instruction pointer, frame pointer, and Local Parameters pointer from a first node to a second node; and (b) performing a procedure on a data structure in accordance with the .mu.thread. The instruction pointer points to an application specific procedure in system memory, and the frame pointer points to an application specific data structure in system memory. The Local Parameters pointer points to one or more words of additional data or parameters stored in memory mapped device registers or system memory.
摘要翻译： 公开了一种用于在并行处理计算机系统的节点之间传送活动消息的方法。 活动消息由mu线程定义，该方法包括以下步骤：（a）从第一节点到第二节点生成包括指令指针，帧指针和本地参数指针的mu线程; 和（b）根据mu线程对数据结构执行一个过程。 指令指针指向系统存储器中的应用程序特定过程，并且帧指针指向系统存储器中的应用程序特定数据结构。 本地参数指针指向存储在存储器映射设备寄存器或系统存储器中的附加数据或参数的一个或多个字。
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公开(公告)号：US5280615A
公开(公告)日：1994-01-18
申请号：US787676
申请日：1991-11-04
CPC分类号： G06F9/3804 , G06F9/384 , G06F9/3851 , G06F9/3853 , G06F9/3863
摘要： A computer system executes steps to provide results in an order different from an intended order. Instructions are concatenated into a plurality of jobs. Different invocations of a variable within the computer instruction stream may be assigned respectively different storage locations and each storage location may correspond to a different job. When all the storage locations associated with a particular job indicate available resources (e.g. valid variable input), the job may be executed. A mechanism allows for job re-execution, if needed, due to interrupt or error.
摘要翻译： 计算机系统执行步骤以提供不同于预期订单的顺序的结果。 指令被连接成多个作业。 计算机指令流中的变量的不同调用可以被分配不同的存储位置，并且每个存储位置可以对应于不同的作业。 当与特定作业相关联的所有存储位置指示可用资源（例如有效变量输入）时，可以执行作业。 如果需要，机制允许由于中断或错误而重新执行作业。
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公开(公告)号：US20180351792A1
公开(公告)日：2018-12-06
申请号：US15613612
申请日：2017-06-05
IPC分类号： H04L12/24
摘要： This application relates in general to a method, apparatus, and article of manufacture for providing secure and redundant communications and processing for a collection of Internet of Things. An extreme way of providing high availability network functionality would be to duplicate every component of the network in a High Availability (HA) style cold standby mode. As long as there is some component, even one that is already in use performing other functions in the IoT network that can pinch hit for the failing component, then uptime can still be achieved and in a more cost effective way than completely duplicate HA fashion.
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5.发明申请公开(公告)号：US20160077937A1
公开(公告)日：2016-03-17
申请号：US14487669
申请日：2014-09-16
申请人： Robert F. Inforzato , Richard E. Blyler , Andrew F. Sanderson , Steven E. Clarke , Dwayne E. Ebersole , Steven L. Forbes , Andrew Ward Beale , Craig F. Russ , Craig R. Church , Derek W. Paul
发明人： Robert F. Inforzato , Richard E. Blyler , Andrew F. Sanderson , Steven E. Clarke , Dwayne E. Ebersole , Steven L. Forbes , Andrew Ward Beale , Craig F. Russ , Craig R. Church , Derek W. Paul
IPC分类号： G06F11/20
CPC分类号： G06F11/2028 , G06F11/2025 , G06F11/2038 , G06F11/2046
摘要： A fabric computer method and system for recovering fabric computer node function. The fabric computer method includes monitoring a processing environment operating on a first Processor and Memory node within the fabric computer complex, detecting a failure of the first Processor and Memory node, and transferring the processing environment from the first Processor and Memory node to a second Processor and Memory node within the fabric computer complex in response to the detection of a failure of the first Processor and Memory node. The fabric computer system includes a first Processor and Memory node, a second Processor and Memory node coupled to the first Processor and Memory node, at least one input/output (I/O) and Networking node coupled to the first and second Processor and Memory nodes, and a fabric manager coupled to the first and second Processor and Memory nodes and the at least one I/O and Networking node. The fabric manager is configured to monitor a processing environment operating on the first Processor and Memory node, to receive notification of a failure of the first Processor and Memory node, and to transfer the processing environment from the first Processor and Memory node to the second Processor and Memory node in response to the detection of a failure of the first Processor and Memory node.
摘要翻译： 一种用于恢复织物计算机节点功能的织物计算机方法和系统。 结构计算机方法包括监视在结构计算机复合体内的第一处理器和存储器节点上操作的处理环境，检测第一处理器和存储器节点的故障，以及将处理环境从第一处理器和存储器节点传送到第二处理器 并且结构计算机内的内存节点复杂以响应检测到第一个处理器和存储器节点的故障。 结构计算机系统包括耦合到第一处理器和存储器节点的第一处理器和存储器节点，第二处理器和存储器节点，耦合到第一和第二处理器和存储器的至少一个输入/输出（I / O）和网络节点 节点和耦合到第一和第二处理器和存储器节点以及至少一个I / O和网络节点的结构管理器。 结构管理器被配置为监视在第一处理器和存储器节点上操作的处理环境，以接收第一处理器和存储器节点的故障的通知，并且将处理环境从第一处理器和存储器节点传送到第二处理器 和Memory节点，以响应检测到第一处理器和存储器节点的故障。
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公开(公告)号：US5506974A
公开(公告)日：1996-04-09
申请号：US115454
申请日：1993-09-02
摘要： A block structured data processing system concatenates block structured code so as to expedite the execution of less structured language code. The concatenation is performed in a code unit for a parallel pipeline processor so that the concatenated code can be executed in parallel. To optimize the access to the data associated with address couples, an address couple associative memory (ACAM) is provided for the translation of conventional address couples found in block structured systems into general registers numbers. The mechanism attempts to keep data in the general registers thus removing the requirement to re-fetch it from the memory system. To expedite the fetching of data arrays, descriptors may be stored in ACAM for use in continuously accessing data arrays in memory.
摘要翻译： 块结构化数据处理系统连接块结构化代码，以便加速较少结构化语言代码的执行。 级联在并行流水线处理器的代码单元中执行，以便并行执行级联代码。 为了优化对与地址对相关联的数据的访问，提供地址对联想存储器（ACAM）用于将在块结构化系统中发现的常规地址对的转换成通用寄存器号。 该机制尝试将数据保留在通用寄存器中，从而消除了从存储器系统重新获取数据的要求。 为了加快获取数据数组，描述符可以存储在ACAM中，用于连续访问存储器中的数据数组。
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