公开(公告)号：US20130094283A1

公开(公告)日：2013-04-18

申请号：US13648221

申请日：2012-10-09

Applicant: CROCUS TECHNOLOGY, INC.

Inventor： Neal Berger ,  Jean-Pierre Nozieres ,  Virgile Javerliac

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C8/08 ,  G11C11/1659 ,  G11C11/1693

Abstract: A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity.

Abstract translation: 一种存储器件包括多个磁性随机存取存储器（MRAM）单元，一个场线，以及一个现场线控制器，被配置为产生穿过场线的写入序列。 写入序列用于将多位字写入多个MRAM单元。 多位字包括具有第一极性的位的第一子集和具有第二极性的位的第二子集。 所述写入顺序并行地写入与具有所述第一极性的所述第一第一子集对应的所述多个MRAM单元的至少一个子集，然后并行地写入所述多个MRAM单元的对应于具有 第二极性。

公开(公告)号：US08902643B2

公开(公告)日：2014-12-02

申请号：US13648221

申请日：2012-10-09

Applicant: Crocus Technology, Inc.

Inventor： Neal Berger ,  Jean-Pierre Nozieres ,  Virgile Javerliac

IPC: G11C11/00 ,  G11C8/08 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G11C8/08 ,  G11C11/1659 ,  G11C11/1693

Abstract: A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity.

Abstract translation: 一种存储器件包括多个磁性随机存取存储器（MRAM）单元，一个场线，以及一个现场线控制器，被配置为产生穿过场线的写入序列。 写入序列用于将多位字写入多个MRAM单元。 多位字包括具有第一极性的位的第一子集和具有第二极性的位的第二子集。 所述写入顺序并行地写入与具有所述第一极性的所述第一第一子集对应的所述多个MRAM单元的至少一个子集，然后并行地写入所述多个MRAM单元的对应于具有 第二极性。