公开(公告)号：US10516044B2

公开(公告)日：2019-12-24

申请号：US14059077

申请日：2013-10-21

申请人： Cypress Semiconductor Corporation

发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

IPC分类号： H01L29/78

摘要： A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.

公开(公告)号：US11830942B2

公开(公告)日：2023-11-28

申请号：US17192512

申请日：2021-03-04

申请人： Cypress Semiconductor Corporation

发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

IPC分类号： H01L29/78 ,  H10B43/30 ,  H10B69/00

CPC分类号： H01L29/78 ,  H10B43/30 ,  H10B69/00

摘要： In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

公开(公告)号：US20220302297A1

公开(公告)日：2022-09-22

申请号：US17192512

申请日：2021-03-04

申请人： Cypress Semiconductor Corporation

发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

IPC分类号： H01L29/78 ,  H01L27/11568 ,  H01L27/115

摘要： In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

公开(公告)号：US20200212215A1

公开(公告)日：2020-07-02

申请号：US16701496

申请日：2019-12-03

申请人： Cypress Semiconductor Corporation

发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

IPC分类号： H01L29/78 ,  H01L27/11568 ,  H01L27/115

摘要： In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

公开(公告)号：US10944000B2

公开(公告)日：2021-03-09

申请号：US16701496

申请日：2019-12-03

申请人： Cypress Semiconductor Corporation

发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

IPC分类号： H01L29/78 ,  H01L27/11568 ,  H01L27/115

摘要： In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.