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    Contacts for semiconductor devices
    3.
    发明授权
    Contacts for semiconductor devices 有权

    公开(公告)号：US11830942B2

    公开(公告)日：2023-11-28

    申请号：US17192512

    申请日：2021-03-04

    申请人： Cypress Semiconductor Corporation

    发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

    IPC分类号： H01L29/78 ,  H10B43/30 ,  H10B69/00

    CPC分类号： H01L29/78 ,  H10B43/30 ,  H10B69/00

    摘要： In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

    CONTACTS FOR SEMICONDUCTOR DEVICES
    4.
    发明申请
    CONTACTS FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220302297A1

    公开(公告)日：2022-09-22

    申请号：US17192512

    申请日：2021-03-04

    申请人： Cypress Semiconductor Corporation

    发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

    IPC分类号： H01L29/78 ,  H01L27/11568 ,  H01L27/115

    摘要： In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

    CONTACTS FOR SEMICONDUCTOR DEVICES
    5.
    发明申请
    CONTACTS FOR SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200212215A1

    公开(公告)日：2020-07-02

    申请号：US16701496

    申请日：2019-12-03

    申请人： Cypress Semiconductor Corporation

    发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

    IPC分类号： H01L29/78 ,  H01L27/11568 ,  H01L27/115

    摘要： In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

    Integrating transistors with different poly-silicon heights on the same die
    6.
    发明授权
    Integrating transistors with different poly-silicon heights on the same die 有权
    将晶体管与不同的多晶硅高度集成在同一芯片上

    公开(公告)号：US09431503B2

    公开(公告)日：2016-08-30

    申请号：US14149521

    申请日：2014-01-07

    申请人： Cypress Semiconductor Corporation

    发明人： Chuan Lin ,  Hidehiko Shiraiwa ,  Bradley Marc Davis ,  Lei Xue ,  Simon S. Chan ,  Kenichi Ohtsuka ,  Angela T. Hui ,  Scott Allan Bell

    IPC分类号： H01L29/49 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/115 ,  H01L21/28

    CPC分类号： H01L29/4916 ,  H01L21/28044 ,  H01L21/823456 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/78

    摘要： An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.

    摘要翻译： 集成电路包括第一多晶硅区域，第一多晶硅区域包括第一多晶硅层，设置在第一多晶硅层上的第二多晶硅层，与第一多晶硅层相关联的第一多硅指状物，以及 与第二多晶硅层相关联的第二多硅指状物。 第一多硅指状物和第二多晶硅指状物相对于彼此以基本上正交的方式取向。 集成电路包括包括第一多晶硅层的第二多晶硅栅极区域。 第一多晶硅栅极区域和第二多晶硅栅极区域各自具有不同的多晶硅栅极结构。

    Contacts for semiconductor devices
    7.
    发明授权
    Contacts for semiconductor devices 有权

    公开(公告)号：US10944000B2

    公开(公告)日：2021-03-09

    申请号：US16701496

    申请日：2019-12-03

    申请人： Cypress Semiconductor Corporation

    发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

    IPC分类号： H01L29/78 ,  H01L27/11568 ,  H01L27/115

    摘要： In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

    Split-gate semiconductor device with L-shaped gate
    8.
    发明授权
    Split-gate semiconductor device with L-shaped gate 有权

    公开(公告)号：US10593688B2

    公开(公告)日：2020-03-17

    申请号：US16023546

    申请日：2018-06-29

    申请人： Cypress Semiconductor Corporation

    发明人： Scott A. Bell ,  Chun Chen ,  Lei Xue ,  Shenqing Fang ,  Angela T. Hui

    IPC分类号： H01L27/1157 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

    摘要： A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.

    Split-gate semiconductor device with L-shaped gate
    9.
    发明授权
    Split-gate semiconductor device with L-shaped gate 有权
    具有L形门的分离栅极半导体器件

    公开(公告)号：US09589805B2

    公开(公告)日：2017-03-07

    申请号：US14450727

    申请日：2014-08-04

    申请人： Cypress Semiconductor Corporation

    发明人： Scott Bell ,  Chun Chen ,  Lei Xue ,  Shenqing Fang ,  Angela T. Hui

    IPC分类号： H01L21/28 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

    CPC分类号： H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

    摘要： A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.

    摘要翻译： 公开了一种半导体器件，其具有衬底，衬底上的电介质层，第一栅极导体，栅极间电介质结构和第二栅极导体。 栅电介质结构设置在第一栅极导体和电介质层之间，并且可以包括以交替方式设置的两个或更多个介电膜。 栅极间电介质结构可以设置在第一栅极导体和第二栅极导体之间​​，并且可以包括以交替方式设置的两个或更多个介电膜。 第二栅极导体形成为L形，使得第二栅极具有相对低的纵横比，这允许相邻栅极之间的间隔减小，同时保持可以随后形成的栅极和触点之间的所需电隔离。