公开(公告)号：US12101945B2

公开(公告)日：2024-09-24

申请号：US18225186

申请日：2023-07-24

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

IPC分类号： H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/408 ,  H01L27/06 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70

CPC分类号： H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L29/24 ,  H01L29/7869 ,  H10B41/20 ,  H10B41/70

摘要： [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US20240266445A1

公开(公告)日：2024-08-08

申请号：US18638923

申请日：2024-04-18

申请人： Samsung Electronics Co., Ltd.

发明人： Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE ,  Seunggeol NAM ,  Sangwook KIM ,  Kwanghee LEE

IPC分类号： H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00

CPC分类号： H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201

摘要： A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US12027643B2

公开(公告)日：2024-07-02

申请号：US17232287

申请日：2021-04-16

申请人： ALEDIA ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Eric Pourquier ,  Hubert Bono

IPC分类号： H01L33/08 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02 ,  H01L27/15 ,  H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/24 ,  H01L33/42 ,  H01L33/48 ,  H10B69/00 ,  H01L33/02

CPC分类号： H01L33/06 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02603 ,  H01L27/15 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/127 ,  H01L29/6609 ,  H01L29/66469 ,  H01L33/0008 ,  H01L33/0062 ,  H01L33/007 ,  H01L33/0095 ,  H01L33/08 ,  H01L33/16 ,  H01L33/18 ,  H01L33/24 ,  H01L33/42 ,  H01L33/48 ,  H10B69/00 ,  H01L33/02 ,  H01L2924/0002 ,  H01L2933/0016 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.

公开(公告)号：US20240188307A1

公开(公告)日：2024-06-06

申请号：US18441204

申请日：2024-02-14

申请人： Kioxia Corporation

发明人： Masahiro KIYOTOSHI ,  Akihito YAMAMOTO ,  Yoshio OZAWA ,  Fumitaka ARAI ,  Riichiro SHIROTA

IPC分类号： H10B63/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/105 ,  H01L29/51 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B69/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/845 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/762 ,  H01L27/105 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B69/00 ,  H10B99/00 ,  H10N70/021 ,  H10N70/231 ,  H10N70/801 ,  H10N70/882 ,  H10N70/028 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

公开(公告)号：US11903205B2

公开(公告)日：2024-02-13

申请号：US17744571

申请日：2022-05-13

申请人： Kioxia Corporation

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H10B43/27 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B69/00 ,  G11C16/04

CPC分类号： H10B43/27 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B69/00 ,  G11C16/0483

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US11869965B2

公开(公告)日：2024-01-09

申请号：US18227183

申请日：2023-07-27

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach

IPC分类号： H01L29/78 ,  G11C16/02 ,  G11C11/404 ,  G11C11/4097 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B69/00 ,  H10B63/00 ,  G11C11/412 ,  G11C16/04

CPC分类号： H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C16/02 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B63/30 ,  H10B69/00 ,  G11C11/412 ,  G11C16/0483 ,  G11C2213/71

摘要： A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; a second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes a global power distribution grid, has a thickness at least twice the second metal layer, and is disposed above third metal layer.

公开(公告)号：US11830942B2

公开(公告)日：2023-11-28

申请号：US17192512

申请日：2021-03-04

申请人： Cypress Semiconductor Corporation

发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

IPC分类号： H01L29/78 ,  H10B43/30 ,  H10B69/00

CPC分类号： H01L29/78 ,  H10B43/30 ,  H10B69/00

摘要： In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

公开(公告)号：US11765912B2

公开(公告)日：2023-09-19

申请号：US17187213

申请日：2021-02-26

申请人： Micron Technology, Inc.

发明人： Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli

IPC分类号： H01L27/24 ,  H01L27/115 ,  H01L45/00 ,  H10B63/00 ,  H10B69/00 ,  H10N70/20 ,  H10N70/00

CPC分类号： H10B63/20 ,  H10B63/30 ,  H10B63/845 ,  H10B69/00 ,  H10N70/20 ,  H10N70/231 ,  H10N70/8828 ,  H10N70/8836

摘要： In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.

公开(公告)号：US11758721B2

公开(公告)日：2023-09-12

申请号：US17202193

申请日：2021-03-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei Cheng Wu ,  Li-Feng Teng

IPC分类号： H10B41/42 ,  H01L29/66 ,  H01L21/28 ,  H10B41/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/44 ,  H10B41/46 ,  H10B41/50 ,  H10B69/00 ,  H01L29/423

CPC分类号： H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H10B41/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/44 ,  H10B41/46 ,  H10B41/50 ,  H10B69/00

摘要： A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US11749348B2

公开(公告)日：2023-09-05

申请号：US17412383

申请日：2021-08-26

申请人： Kioxia Corporation

发明人： Hiroki Date

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/08 ,  G11C16/30 ,  H10B69/00

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/3459 ,  H10B69/00

摘要： A semiconductor storage device includes: a plurality of first memory cells; a word line connected to gates of the first memory cells; a voltage generation circuit configured to generate voltage to be supplied to the word line on the basis of a set value; and a control unit configured to execute a write sequence that includes a plurality of loops, each loop including a program operation to increase a threshold voltage of at least part of the first memory cells to thereby write data to the first memory cells and a verify operation to verify the data written to the first memory cells. The voltage generation circuit generates voltage to be supplied to the word line at start of the verify operation on the basis of a first set value, and the control unit adjusts the first set value in accordance with progress of the write sequence.