公开(公告)号：US20230223858A1

公开(公告)日：2023-07-13

申请号：US17575001

申请日：2022-01-13

Applicant: Cypress Semiconductor Corporation

Inventor： Pulkit SHAH ,  Arun KHAMESRA ,  Hariom RAI

IPC: H02M3/335 ,  H02M1/08 ,  H02M1/00

CPC classification number: H02M3/33592 ,  H02M1/08 ,  H02M1/0012

Abstract: A secondary-side-controller for a QR flyback converter and method for operating the same are provided. Generally, the secondary-side-controller includes a driver configured to control a power-switch (PS) on a primary side of converter to turn on the PS when a sinusoidal input voltage to the converter is at one of a plurality of valleys, an analog-to-digital-converter (ADC) to read the input voltage, output voltage, and load current, and generate digital signals based thereon. A valley-controller coupled to the driver, ADC, a look-up-table and a pulse width modulator (PWM) receives the signals from the ADC and using the look-up-table determines at which valley of the plurality of valleys to couple a PWM signal from the PWM to the driver. The valley-controller is operable for each switching cycle of the PS to increment, decrement or leave unchanged the valley at which the PWM signal is coupled from the PWM to the driver.

公开(公告)号：US20240427722A1

公开(公告)日：2024-12-26

申请号：US18339989

申请日：2023-06-22

Applicant: Cypress Semiconductor Corporation

Inventor： Arun KHAMESRA ,  Hariom RAI ,  Pulkit SHAH

IPC: G06F13/40 ,  G06F1/26

Abstract: Techniques are provided for discharge of a universal serial bus voltage. A determination is made that the universal serial bus voltage has exceeded a threshold. Accordingly, initiation of a discharge operation is triggered to discharge the universal serial bus voltage. The discharge operation includes applying incrementally increasing voltage reference values according to a periodic interval to an amplifier until a discharge trigger point is reached. The amplifier outputs a voltage signal to a gate driver that controls a gate of a transistor that provides a discharge path for the universal serial bus voltage to discharge. In response to reaching the discharge trigger point, the incremental increasing of the voltage reference values applied to the amplifier is stopped.

公开(公告)号：US20230344213A1

公开(公告)日：2023-10-26

申请号：US17730028

申请日：2022-04-26

Applicant: Cypress Semiconductor Corporation

Inventor： Arun Khamesra ,  Hariom RAI ,  Pulkit SHAH

IPC: H02H3/06 ,  H02H3/08

CPC classification number: H02H3/06 ,  H02H3/08

Abstract: A system includes a first USB Type-C Power Delivery (USB-C/PD) port and a control circuit operatively coupled to the first USB-C/PD port. The control circuit is configured to determine whether a short circuit condition has occurred based on a first threshold voltage. The control circuit is also configured to turn off a ground isolation switch when short circuit condition occurs. The control circuit is further configured to determine a whether a voltage on a ground line is less than a second threshold voltage. The control circuit is further configured to turn on the ground isolation switch when the voltage on the ground line is less than the second threshold voltage. The control circuit may perform one or more error recovery operations after turning on the ground isolation switch.

公开(公告)号：US20230299676A1

公开(公告)日：2023-09-21

申请号：US17696781

申请日：2022-03-16

Applicant: Cypress Semiconductor Corporation

Inventor： Hemant P. Vispute ,  Partha MONDAL ,  Tudu Rushika Banam BALIA ,  Arun KHAMESRA ,  Pulkit SHAH ,  Hariom RAI

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

CPC classification number: H02M3/1582 ,  H02M1/0012 ,  H02M1/08

Abstract: Universal Serial Bus Type-C (USB-C) controllers with a floating gate driver with programmable drive strength for a wide range of USB power delivery applications in electronic devices described. A USB-C controller includes a floating gate driver and control logic. The floating gate driver includes p-channel field-effect transistors (FETs) coupled in parallel between a first terminal and a second terminal and p-channel pre-gate drivers. Each p-channel pre-gate driver is coupled to a gate of one of the p-channel FETs. The floating gate driver includes n-channel FETs coupled in parallel between the second terminal and a third terminal and n-channel pre-gate drivers, each n-channel pre-gate driver being coupled to a gate of one of the plurality of n-channel FETs. The control logic sends one or more control signals to activate a first number of p-channel pre-gate drivers and a second number of n-channel pre-gate drivers based on an output voltage.