公开(公告)号：US20200073568A1

公开(公告)日：2020-03-05

申请号：US16116002

申请日：2018-08-29

申请人： DELL PRODUCTS L.P.

发明人： Craig Chaiken ,  Michael Arms ,  Vinod Makhija ,  Stephen Cooper

IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F13/42

摘要： Systems and methods are provided for creating and/or modifying memory configuration settings (e.g., such as memory timing and memory drive voltage) for use at selected and/or varying memory temperature/s. The disclosed systems and methods may be implemented to create a relationship between optimized memory configuration settings for different memory temperatures during burn-in testing and/or on an ad-hoc basis.

公开(公告)号：US11487621B1

公开(公告)日：2022-11-01

申请号：US17244624

申请日：2021-04-29

申请人： Dell Products L.P.

发明人： Adolfo Montero ,  Michael Arms ,  Balasingh P. Samuel

IPC分类号： G06F11/14 ,  G06F11/27 ,  G06F21/54 ,  G06F11/07 ,  G06F21/57 ,  G06F11/30

摘要： An information handling system may include at least one processor, a memory, and an embedded controller (EC). The information handling system may be configured to, prior to initialization of an operating system of the information handling system: execute memory reference code configured to test selected regions of the memory; transmit results of the memory reference code to the EC; store, at the EC, information indicative of respective likelihoods that particular regions of the memory are bad; and upon a subsequent boot, select a region of the memory having a low likelihood of being bad for loading a Basic Input/Output System (BIOS) of the information handling system.

公开(公告)号：US10782900B2

公开(公告)日：2020-09-22

申请号：US16116002

申请日：2018-08-29

申请人： DELL PRODUCTS L.P.

发明人： Craig Chaiken ,  Michael Arms ,  Vinod Makhija ,  Stephen Cooper

IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F13/42

摘要： Systems and methods are provided for creating and/or modifying memory configuration settings (e.g., such as memory timing and memory drive voltage) for use at selected and/or varying memory temperature/s. The disclosed systems and methods may be implemented to create a relationship between optimized memory configuration settings for different memory temperatures during burn-in testing and/or on an ad-hoc basis.