公开(公告)号：US20190392289A1

公开(公告)日：2019-12-26

申请号：US16561207

申请日：2019-09-05

Applicant: DENSO CORPORATION

Inventor： Shigeki OTSUKA ,  Irina KATAEVA

IPC: G06N3/04 ,  G11C13/00 ,  H03F3/45 ,  G06F7/544

Abstract: A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion amplification circuits for converting currents flowing via the memory elements into voltages, a differential amplifier circuit for performing a differential operation on outputs of two I-V conversion amplification circuits, an A-D converter for performing an A-D conversion on a result of the differential operation, and an output determine that, by referring to input signals of the differential amplifier circuit, determines whether an output signal value of the differential amplifier circuit belongs to an active region or an inactive region. Based on a determination result, the input determiner switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.

公开(公告)号：US20200082255A1

公开(公告)日：2020-03-12

申请号：US16688088

申请日：2019-11-19

Applicant: DENSO CORPORATION

Inventor： Irina KATAEVA

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/15

Abstract: A convolutional neural network includes: convolution layers and a merging layer. At least one convolution layer includes a crossbar circuit having input bars, output bars and weight assignment elements that assign weights to input signals. The crossbar circuit performs a convolution operation in an analog region with respect to input data including the input signal by adding the input signals at each output bar. The input data includes feature maps. The crossbar circuit includes a first crossbar circuit for performing the convolution operation with respect to a part of the feature maps and a second crossbar circuit for performing the convolution operation with respect to another part of feature maps. The merging layer merges convolution operation results of the first and second crossbar circuits.

公开(公告)号：US20190332927A1

公开(公告)日：2019-10-31

申请号：US16379355

申请日：2019-04-09

Applicant: DENSO CORPORATION

Inventor： Shigeki OTSUKA ,  Irina KATAEVA

IPC: G06N3/063 ,  H03M1/46

Abstract: A neural network circuit includes: a storage portion that includes memristors; D/A converters; drive amplifiers; I/V conversion amplifiers; A/D converters; and offset correctors. The offset corrector includes a first latch circuit, a second latch circuit, a subtractor that subtracts latch data, and a controller. In performing a bias setting operation, the controller controls a bias application amplifier to output the bias voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output a reference voltage, and also cause the first latch circuit to latch the output data. In performing a normal operation, the controller controls the bias application amplifier to output the reference voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output the signal voltage, and also cause the second latch circuit to latch the output data.

公开(公告)号：US20190147330A1

公开(公告)日：2019-05-16

申请号：US16249190

申请日：2019-01-16

Applicant: DENSO CORPORATION

Inventor： Shigeki OTSUKA ,  Hironobu AKITA ,  Irina KATAEVA

IPC: G06N3/063 ,  G11C11/54 ,  G11C13/00

Abstract: A neural network circuit includes: a storage part that includes memristors in a lattice shape; a voltage application circuit that applies a bias voltage to the storage part; a controller that controls the voltage application circuit to perform to a selection element, writing, erasing, or reading; and multiple conversion amplification circuits that convert a current flowing into a voltage, and output the voltage.

公开(公告)号：US20170017879A1

公开(公告)日：2017-01-19

申请号：US14797284

申请日：2015-07-13

Applicant: DENSO CORPORATION ,  The Regents of the University of California

Inventor： Irina KATAEVA ,  Dmitri B. STRUKOV ,  Farnood MERRIKH-BAYAT

IPC: G06N3/08 ,  G06F11/07

CPC classification number: G06N3/084 ,  G06F11/0721 ,  G06F11/079 ,  G06N3/063

Abstract: A neural network is implemented as a memristive neuromorphic circuit that includes a neuron circuit and a memristive device connected to the neuron circuit. An input voltage is sensed at a first terminal of a memristive device during a feedforward operation of the neural network. An error voltage is sensed at a second terminal of the memristive device during an error backpropagation operation of the neural network. In accordance with a training rule, a desired conductance change for the memristive device is computed based on the sensed input voltage and the sensed error voltage. Then a training voltage is applied to the memristive device. Here, the training voltage is proportional to a logarithmic value of the desired conductance change.

Abstract translation: 神经网络被实现为包含神经元电路和连接到神经元电路的忆阻器的忆阻神经电路。 在神经网络的前馈操作期间，在忆阻器件的第一端子处感测输入电压。 在神经网络的误差反向传播操作期间，在忆阻器件的第二端子处感测到误差电压。 根据训练规则，基于检测到的输入电压和感测到的误差电压来计算忆阻器件的期望的电导变化。 然后将训练电压施加到忆阻器上。 这里，训练电压与期望的电导变化的对数值成比例。

公开(公告)号：US20170017877A1

公开(公告)日：2017-01-19

申请号：US14797266

申请日：2015-07-13

Applicant: DENSO CORPORATION ,  The Regents of the University of California

Inventor： Irina KATAEVA ,  Dmitri B. STRUKOV ,  Farnood MERRIKH-BAYAT

IPC: G06N3/063 ,  G06N3/08

CPC classification number: G06N3/0635 ,  G06N3/08 ,  G06N3/084

Abstract: A neural network is implemented as a memristive neuromorphic circuit that includes a neuron circuit and a memristive device connected to the neuron circuit. A conductance balanced voltage pair is provided for the memristive device, where the conductance balanced voltage pair includes a set voltage for increasing the conductance of the memristive device and a reset voltage for decreasing the conductance of the memristive device. Either the set voltage and reset voltage, when applied to the memristive device, effects a substantially same magnitude conductance change in the memristive device over a predetermined range of conductance of the memristive device. The provided voltage pair is stored as a conductance balanced map. A training voltage based on the conductance balanced map is applied to the memristive device to train the neural network.

Abstract translation: 神经网络被实现为包含神经元电路和连接到神经元电路的忆阻器的忆阻神经电路。 为忆阻器件提供电导平衡电压对，其中电导平衡电压对包括用于增加忆阻器件的电导的设定电压和用于降低忆阻器件的电导的复位电压。 当施加到忆阻器件时，设定电压和复位电压在忆阻器件的预定电导范围内在忆阻器件中产生基本上相同的幅度电导变化。 提供的电压对作为电导平衡图存储。 基于电导平衡图的训练电压被应用于忆阻器来训练神经网络。