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公开(公告)号：US20220085719A1
公开(公告)日：2022-03-17
申请号：US17472913
申请日：2021-09-13
Applicant: DENSO CORPORATION
Inventor： Shigeki OTSUKA , Naoto KIKUCHI
Abstract: A signal generation circuit includes: a capacitor charged and discharged by a current proportional to an input voltage; a switch controlling charging and discharging of the capacitor based on an output signal of a comparator that compares a feedback voltage according to an output voltage and a predetermined first reference voltage; a reference voltage generation unit generating a second reference voltage that is generated by adding an offset voltage proportional to the input voltage to an output proportional voltage proportional to the output voltage; and a comparator comparing a terminal voltage of the capacitor and the second reference voltage, and generates an ON-time signal based on an output signal of the comparator.
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公开(公告)号：US20180302122A1
公开(公告)日：2018-10-18
申请号：US15770507
申请日：2016-11-28
Applicant: DENSO CORPORATION
Inventor： Chao CHEN , Shigeki OTSUKA
Abstract: A transmission-path degradation detection apparatus comprises a transmission path of a transmission system, plural communication devices connected to the transmission path, a signal generation part provided in one communication device of the plural communication devices for generating a pseudo-communication signal, and a degradation detection part provided in one communication device of the plural communication devices for detecting a degradation of the transmission path based on a reception of the pseudo-communication signal passing through the transmission path.
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公开(公告)号：US20230062515A1
公开(公告)日：2023-03-02
申请号：US17868057
申请日：2022-07-19
Inventor： Shigeki OTSUKA , Hyoungjun NA , Takasuke ITO , Yoshikazu FURUTA , Tomohiro NEZUKA
IPC: H04L25/02 , H03K17/687
Abstract: A differential transmission circuit for a communication device performs bidirectional communication via a differential transmission line. The differential transmission circuit include: output transistors that are turned on and off according to a drive signal during a transmission period; a signal generation unit that generates and outputs the drive signal; short-circuit transistors connected between gates and drains of the output transistors; and a cut off unit that cuts off a supply path of the drive signal between the signal generation unit and the gates of the output transistors. The cut off unit cuts off the supply path of the drive signal during a reception period in which a reception operation is performed by the communication device.
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公开(公告)号：US20220340011A1
公开(公告)日：2022-10-27
申请号：US17722444
申请日：2022-04-18
Inventor： Hyoungjun NA , Yoshikazu FURUTA , Shigeki OTSUKA , Takasuke ITO , Tomohiro NEZUKA
Abstract: In a communication system, a control unit and driver units are connected in a daisy chain; each unit includes a corresponding insulated communication circuit, respectively. The control unit measures a communication delay time between the control unit and each driver unit from a response time to transmission of a pulse signal performed to each driver unit during a measurement period. Then, based on each communication delay time, the control unit transmits a shift time to each driver unit for equalizing the timing of signals output by the driver units. When each driver unit receives, from the control unit, an instruction instructing each driver unit to output a signal, each driver unit outputs the signal when the shift time has elapsed.
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公开(公告)号：US20190147330A1
公开(公告)日：2019-05-16
申请号：US16249190
申请日：2019-01-16
Applicant: DENSO CORPORATION
Inventor： Shigeki OTSUKA , Hironobu AKITA , Irina KATAEVA
Abstract: A neural network circuit includes: a storage part that includes memristors in a lattice shape; a voltage application circuit that applies a bias voltage to the storage part; a controller that controls the voltage application circuit to perform to a selection element, writing, erasing, or reading; and multiple conversion amplification circuits that convert a current flowing into a voltage, and output the voltage.
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Patent Agency Ranking
公开(公告)号：US20220321387A1
公开(公告)日：2022-10-06
申请号：US17705631
申请日：2022-03-28
Applicant: DENSO CORPORATION
Inventor： Takasuke ITO , Yoshikazu FURUTA , Shigeki OTSUKA , Tomohiro NEZUKA
IPC: H04L25/02 , H04B1/04 , H03K19/0185 , H03K19/20
Abstract: A differential communication driver circuit includes a drive unit that drives differential signal lines connected via capacitors by a source current and a sink current. When a noise detection unit detects that in-phase noise is applied to the differential signal lines, a drive assisting unit maintains an amplitude of a differential signal output to the differential signal lines by increasing a current drive capability of the sink current.
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公开(公告)号：US20210159778A1
公开(公告)日：2021-05-27
申请号：US17091130
申请日：2020-11-06
Applicant: DENSO CORPORATION
Inventor： Shigeki OTSUKA
Abstract: A short-circuit determination device is provided in a switching power supply device. The switching power supply device converts a power supply voltage applied between an upper power supply line and a lower power supply line and outputs the power supply voltage to a load through an intermediate node. The switching power supply device includes a plurality of upper switching elements and a lower switching element. Each of the plurality of upper switching elements has an electrical conduction terminal and a control terminal. The electrical conduction terminals are connected in series between the upper power supply line and the intermediate node. The control terminals are driven at a same level as each other. The lower switching element has an electrical conduction terminal connected between the lower power supply line and the intermediate node. The lower switching element and the plurality of upper switching elements are connected in series.
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公开(公告)号：US20190392290A1
公开(公告)日：2019-12-26
申请号：US16562534
申请日：2019-09-06
Applicant: DENSO CORPORATION
Inventor： Shigeki OTSUKA
Abstract: A neural network circuit includes a memory device in which memristors being variable resistance elements are connected in a matrix and serve as memory elements of the memory device. The neural network circuit further includes a voltage application device arranged to apply a bias voltage to the memory device and current-voltage (I-V) conversion amplification circuits arranged to convert currents flowing via the memory elements into voltages and output the voltage. A feedback resistor of a respective I-V conversion amplification circuit includes a memristor. The feedback resistor of a respective I-V conversion amplification circuit and the memory elements acting as an input resistor of the I-V conversion amplification circuit are connected to align a polarity direction of the memristor of the feedback resistor and polarity directions of the memristors of the memory elements acting as the input resistor.
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公开(公告)号：US20190392289A1
公开(公告)日：2019-12-26
申请号：US16561207
申请日：2019-09-05
Applicant: DENSO CORPORATION
Inventor： Shigeki OTSUKA , Irina KATAEVA
Abstract: A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion amplification circuits for converting currents flowing via the memory elements into voltages, a differential amplifier circuit for performing a differential operation on outputs of two I-V conversion amplification circuits, an A-D converter for performing an A-D conversion on a result of the differential operation, and an output determine that, by referring to input signals of the differential amplifier circuit, determines whether an output signal value of the differential amplifier circuit belongs to an active region or an inactive region. Based on a determination result, the input determiner switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.
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公开(公告)号：US20240243743A1
公开(公告)日：2024-07-18
申请号：US18537108
申请日：2023-12-12
Inventor： Takasuke ITO , Shigeki OTSUKA , Yoshikazu FURUTA , Tomohiro NEZUKA
IPC: H03K17/687 , H03K19/20
CPC classification number: H03K17/6871 , H03K19/20
Abstract: A deterioration inhibiting circuit includes a switchover circuit that inhibits characteristic deterioration of first and second transistors included in a differential pair circuit having first and second input terminals. A gate of the first transistor is connected to the first input terminal, and a gate of the second transistor is connected to the second input terminal. The switchover circuit executes switchover between a first state and a second state. In the first state, a first voltage is applied to the gate of the first transistor and a second voltage is applied to the gate of the second transistor. In the second state, the second voltage is applied to the gate of the first transistor and the first voltage is applied to the gate of the second transistor. the first voltage is higher than an intermediate voltage, and the second voltage is lower than the intermediate voltage.
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