公开(公告)号：US20190109187A1

公开(公告)日：2019-04-11

申请号：US16093882

申请日：2017-04-18

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Tadashi MISUMI ,  Hiroomi EGUCHI ,  Yusuke YAMASHITA ,  Yasushi URAKAMI

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L29/66

Abstract: A switching element including: a bottom insulating layer disposed at a bottom of a trench; a side surface insulating film covering a side surface of the trench; and a gate electrode disposed inside the trench and insulated from a semiconductor substrate. The semiconductor substrate has a bottom region and a connection region. The bottom region is in contact with the bottom insulating layer. The connection region is in contact with the bottom insulating layer and the side surface insulating film, and connects a body region to the bottom region. An area of the connection region in which the bottom insulating layer contacts to the connection region includes an area with lower a second conductivity-type impurity concentration than a minimum value of the second conductivity-type impurity concentration in an area of the connection region in which the side surface insulating film contacts the connection region.

公开(公告)号：US20200161467A1

公开(公告)日：2020-05-21

申请号：US16729733

申请日：2019-12-30

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI ,  Shuhei MITANI ,  Yasuhiro EBIHARA ,  Yusuke YAMASHITA ,  Tadashi MISUMI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16

Abstract: A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.