公开(公告)号：US20140104936A1

公开(公告)日：2014-04-17

申请号：US14051357

申请日：2013-10-10

Applicant: DOLPHIN INTEGRATION

Inventor： Ilan Sever

IPC: G11C11/412 ,  G11C29/08

CPC classification number: G11C11/412 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/418 ,  G11C11/419 ,  G11C29/08

Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

Abstract translation: 本发明涉及具有以列和行排列的存储单元的存储器阵列，每列的存储单元耦合到其列的至少一个公共写入线，每行的存储单元耦合到其行的公共选择行 其中每个存储单元包括由在第一和第二存储节点之间交叉耦合的一对反相器形成的锁存器; 耦合在第一存储节点和第一测试数据输入之间的第一晶体管; 以及耦合在所述第二存储节点和第二测试数据输入之间的第二晶体管。

公开(公告)号：US09269423B2

公开(公告)日：2016-02-23

申请号：US14051357

申请日：2013-10-10

Applicant: DOLPHIN INTEGRATION

Inventor： Ilan Sever

IPC: G11C7/10 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/08 ,  G11C7/22

CPC classification number: G11C11/412 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/418 ,  G11C11/419 ,  G11C29/08

Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

Abstract translation: 本发明涉及具有以列和行排列的存储单元的存储器阵列，每列的存储单元耦合到其列的至少一个公共写入线，每行的存储单元耦合到其行的公共选择行 其中每个存储单元包括由在第一和第二存储节点之间交叉耦合的一对反相器形成的锁存器; 耦合在第一存储节点和第一测试数据输入之间的第一晶体管; 以及耦合在所述第二存储节点和第二测试数据输入之间的第二晶体管。