公开(公告)号：US20090152599A1

公开(公告)日：2009-06-18

申请号：US12234393

申请日：2008-09-19

申请人： Da Wei Gao ,  Bei Zhu ,  Hanming Wu ,  John Chen ,  Paolo Bonfanti

发明人： Da Wei Gao ,  Bei Zhu ,  Hanming Wu ,  John Chen ,  Paolo Bonfanti

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

摘要： An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region. Depending upon the embodiment, the fill material can be any suitable species such as silicon germanium, silicon carbide, and others.

摘要翻译： 集成电路半导体器件，例如MOS，CMOS。 该器件具有半导体衬底。 该器件还具有覆盖半导体衬底的电介质层和覆盖在介电层上的栅极结构。 电介质层在栅极结构的边缘上形成侧壁间隔物。 凹陷区域在侧壁间隔结构内的栅极结构的一部分内。 外延填充材料在凹陷区域内。 该器件在半导体衬底内具有源极凹陷区域和漏极凹陷区域，并且耦合到栅极结构。 该器件在源极凹陷区域内和漏极凹陷区域内具有外延填充材料。 源极区域和漏极区域之间的沟道区域至少从形成在源极区域和漏极区域中的填充材料的应变特性中得到。 根据实施例，填充材料可以是任何合适的物质，例如硅锗，碳化硅等。

公开(公告)号：US20080173941A1

公开(公告)日：2008-07-24

申请号：US11678582

申请日：2007-02-24

申请人： Bei Zhu ,  Paolo Bonfanti ,  Hanming Wu ,  Da Wei Gao ,  John Chen

发明人： Bei Zhu ,  Paolo Bonfanti ,  Hanming Wu ,  Da Wei Gao ,  John Chen

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor integrated circuit device comprising a semiconductor substrate, e.g., silicon wafer, silicon on insulator. The device has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. The device also has a channel region within a portion of the semiconductor substrate within a vicinity of the gate structure and a lightly doped source/drain regions in the semiconductor substrate to from diffused pocket regions underlying portions of the gate structure. The device has sidewall spacers on edges of the gate structure. The device also has an etched source region and an etched drain region. Each of the first source region and the first drain region is characterized by a recessed region having substantially vertical walls, a bottom region, and rounded corner regions connecting the vertical walls to the bottom region.

摘要翻译： 一种半导体集成电路器件，包括半导体衬底，例如硅晶片，绝缘体上硅。 该器件具有覆盖半导体衬底的电介质层和覆盖该介电层的栅极结构。 器件还在栅极结构附近的半导体衬底的一部分内部具有通道区域，以及半导体衬底中的轻掺杂源极/漏极区域，以从栅极结构的部分下方的扩散袋区域。 该装置在栅极结构的边缘上具有侧壁间隔物。 该器件还具有蚀刻源极区和蚀刻漏极区。 第一源极区域和第一漏极区域中的每一个的特征在于具有基本上垂直的壁的凹陷区域，底部区域和将垂直壁连接到底部区域的圆角区域。

公开(公告)号：US20080119032A1

公开(公告)日：2008-05-22

申请号：US11609748

申请日：2006-12-12

申请人： John Chen ,  Hanming Wu ,  Da Wei Gao ,  Bei Zhu ,  Paolo Bonfanti

发明人： John Chen ,  Hanming Wu ,  Da Wei Gao ,  Bei Zhu ,  Paolo Bonfanti

IPC分类号： H01L21/3205

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  Y10S438/938

摘要： A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a hard mask overlying the gate layer. The method patterns the gate layer to form a gate structure including edges using the hard mask as a protective layer. The method forms a dielectric layer overlying the gate structure to protect the gate structure including the edges. The method forms spacers from the dielectric layer, while maintaining the hard mask overlying the gate structure. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer and the hard mask as a protective layer, while the hard mask prevents any portion of the gate structure from being exposed. In a preferred embodiment, the method maintains the hard mask overlying the gate structure. The method includes depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region, while maintaining any portion of the gate layer from being exposed using the hard mask such that the gate structure is substantially free from any permanent deposition of silicon germanium material, which causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. In a preferred embodiment, the method removing the hard mask from the gate structure to expose a top portion of the gate structure and maintains the top portion of the gate structure being substantially free from any silicon germanium material.

摘要翻译： 一种形成应变硅集成电路器件的方法。 该方法包括提供半导体衬底并形成覆盖半导体衬底的电介质层。 该方法还包括形成覆盖在电介质层上的栅极层，并形成覆盖栅极层的硬掩模。 该方法使栅极层形成包括使用硬掩模的边缘作为保护层的栅极结构。 该方法形成覆盖栅极结构的电介质层，以保护包括边缘的栅极结构。 该方法从电介质层形成间隔物，同时保持覆盖栅极结构的硬掩模。 该方法使用电介质层和硬掩模作为保护层来蚀刻与栅极结构相邻的源极区域和漏极区域，同时硬掩模防止栅极结构的任何部分暴露。 在优选实施例中，该方法保持覆盖栅极结构的硬掩模。 该方法包括将硅锗材料沉积到源极区域和漏极区域中以填充蚀刻的源极区域和蚀刻的漏极区域，同时保持栅极层的任何部分不被使用硬掩模曝光，使得栅极结构基本上是空的 来自硅锗材料的任何永久性沉积，其使得源极区域和漏极区域之间的沟道区域至少在形成于源极区域和漏极区域中的硅锗材料以压缩模式应变。 在优选实施例中，该方法从栅极结构去除硬掩模以露出栅极结构的顶部并且保持栅极结构的顶部基本上不含任何硅锗材料。

公开(公告)号：US08551831B2

公开(公告)日：2013-10-08

申请号：US12234393

申请日：2008-09-19

申请人： Da Wei Gao ,  Bei Zhu ,  Hanming Wu ,  John Chen ,  Paolo Bonfanti

发明人： Da Wei Gao ,  Bei Zhu ,  Hanming Wu ,  John Chen ,  Paolo Bonfanti

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

摘要： An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region. Depending upon the embodiment, the fill material can be any suitable species such as silicon germanium, silicon carbide, and others.

摘要翻译： 集成电路半导体器件，例如MOS，CMOS。 该器件具有半导体衬底。 该器件还具有覆盖半导体衬底的电介质层和覆盖在介电层上的栅极结构。 电介质层在栅极结构的边缘上形成侧壁间隔物。 凹陷区域在侧壁间隔结构内的栅极结构的一部分内。 外延填充材料在凹陷区域内。 该器件在半导体衬底内具有源极凹陷区域和漏极凹陷区域，并且耦合到栅极结构。 该器件在源极凹陷区域内和漏极凹陷区域内具有外延填充材料。 源极区域和漏极区域之间的沟道区域至少从形成在源极区域和漏极区域中的填充材料的应变特性中得到。 根据实施例，填充材料可以是任何合适的物质，例如硅锗，碳化硅等。

公开(公告)号：US07557000B2

公开(公告)日：2009-07-07

申请号：US11609748

申请日：2006-12-12

申请人： John Chen ,  Hanming Wu ,  Da Wei Gao ,  Bei Zhu ,  Paolo Bonfanti

发明人： John Chen ,  Hanming Wu ,  Da Wei Gao ,  Bei Zhu ,  Paolo Bonfanti

IPC分类号： H01L21/8238

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  Y10S438/938

摘要： A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a hard mask overlying the gate layer. The method patterns the gate layer to form a gate structure including edges using the hard mask as a protective layer. The method forms a dielectric layer overlying the gate structure to protect the gate structure including the edges. The method forms spacers from the dielectric layer, while maintaining the hard mask overlying the gate structure. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer and the hard mask as a protective layer, while the hard mask prevents any portion of the gate structure from being exposed. In a preferred embodiment, the method maintains the hard mask overlying the gate structure. The method includes depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region, while maintaining any portion of the gate layer from being exposed using the hard mask such that the gate structure is substantially free from any permanent deposition of silicon germanium material, which causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. In a preferred embodiment, the method removing the hard mask from the gate structure to expose a top portion of the gate structure and maintains the top portion of the gate structure being substantially free from any silicon germanium material.

摘要翻译： 一种形成应变硅集成电路器件的方法。 该方法包括提供半导体衬底并形成覆盖半导体衬底的电介质层。 该方法还包括形成覆盖在电介质层上的栅极层，并形成覆盖栅极层的硬掩模。 该方法使栅极层形成包括使用硬掩模的边缘作为保护层的栅极结构。 该方法形成覆盖栅极结构的电介质层，以保护包括边缘的栅极结构。 该方法从电介质层形成间隔物，同时保持覆盖栅极结构的硬掩模。 该方法使用电介质层和硬掩模作为保护层来蚀刻与栅极结构相邻的源极区域和漏极区域，同时硬掩模防止栅极结构的任何部分暴露。 在优选实施例中，该方法保持覆盖栅极结构的硬掩模。 该方法包括将硅锗材料沉积到源极区域和漏极区域中以填充蚀刻的源极区域和蚀刻的漏极区域，同时保持栅极层的任何部分不被使用硬掩模曝光，使得栅极结构基本上是空的 来自硅锗材料的任何永久性沉积，其使得源极区域和漏极区域之间的沟道区域至少在形成于源极区域和漏极区域中的硅锗材料以压缩模式应变。 在优选实施例中，该方法从栅极结构去除硬掩模以露出栅极结构的顶部并且保持栅极结构的顶部基本上不含任何硅锗材料。