摘要:
A semiconductor integrated circuit device comprising a semiconductor substrate, e.g., silicon wafer, silicon on insulator. The device has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. The device also has a channel region within a portion of the semiconductor substrate within a vicinity of the gate structure and a lightly doped source/drain regions in the semiconductor substrate to from diffused pocket regions underlying portions of the gate structure. The device has sidewall spacers on edges of the gate structure. The device also has an etched source region and an etched drain region. Each of the first source region and the first drain region is characterized by a recessed region having substantially vertical walls, a bottom region, and rounded corner regions connecting the vertical walls to the bottom region.
摘要:
A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a hard mask overlying the gate layer. The method patterns the gate layer to form a gate structure including edges using the hard mask as a protective layer. The method forms a dielectric layer overlying the gate structure to protect the gate structure including the edges. The method forms spacers from the dielectric layer, while maintaining the hard mask overlying the gate structure. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer and the hard mask as a protective layer, while the hard mask prevents any portion of the gate structure from being exposed. In a preferred embodiment, the method maintains the hard mask overlying the gate structure. The method includes depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region, while maintaining any portion of the gate layer from being exposed using the hard mask such that the gate structure is substantially free from any permanent deposition of silicon germanium material, which causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. In a preferred embodiment, the method removing the hard mask from the gate structure to expose a top portion of the gate structure and maintains the top portion of the gate structure being substantially free from any silicon germanium material.
摘要:
An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region. Depending upon the embodiment, the fill material can be any suitable species such as silicon germanium, silicon carbide, and others.
摘要:
An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region. Depending upon the embodiment, the fill material can be any suitable species such as silicon germanium, silicon carbide, and others.
摘要:
A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a hard mask overlying the gate layer. The method patterns the gate layer to form a gate structure including edges using the hard mask as a protective layer. The method forms a dielectric layer overlying the gate structure to protect the gate structure including the edges. The method forms spacers from the dielectric layer, while maintaining the hard mask overlying the gate structure. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer and the hard mask as a protective layer, while the hard mask prevents any portion of the gate structure from being exposed. In a preferred embodiment, the method maintains the hard mask overlying the gate structure. The method includes depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region, while maintaining any portion of the gate layer from being exposed using the hard mask such that the gate structure is substantially free from any permanent deposition of silicon germanium material, which causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. In a preferred embodiment, the method removing the hard mask from the gate structure to expose a top portion of the gate structure and maintains the top portion of the gate structure being substantially free from any silicon germanium material.
摘要:
A method for forming a semiconductor integrated circuit device, e.g., MOS, CMOS. The method includes providing a semiconductor substrate, e.g., silicon substrate, silicon on insulator. The method includes forming a dielectric layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the semiconductor substrate. The method also includes forming a gate layer (e.g., polysilicon) overlying the dielectric layer. The method patterns the gate layer to form a gate structure including edges. The method includes forming a dielectric layer overlying the gate structure to protect the gate structure including the edges. In a specific embodiment, sidewall spacers are formed using portions of the dielectric layer. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer. In a preferred embodiment, the method deposits using selective epi growth of silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region and simultaneously introduces a dopant impurity species into the silicon germanium material during a portion of the time associated with the depositing of the silicon germanium material to dope the silicon germanium material during the portion of the time associated with the depositing of the silicon germanium material. In a specific embodiment, the method also includes causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region.
摘要:
A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).
摘要:
A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the gate structure to protect the gate structure including the edges. An exposed portion of the metal hard mask layer is overlying the gate structure. A silicon germanium fill material is provided in an etched source region and an etched drain region. The etched source region and the etched drain region are each coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the silicon germanium material formed in the etched source region and the etched drain region. An electrical connection is coupled to the metal hard mask overlying the gate structure. Optionally, the device has a second metal layer overlying the metal hard mask.
摘要:
A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the gate structure to protect the gate structure including the edges. An exposed portion of the metal hard mask layer is overlying the gate structure. A silicon germanium fill material is provided in an etched source region and an etched drain region. The etched source region and the etched drain region are each coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the silicon germanium material formed in the etched source region and the etched drain region. An electrical connection is coupled to the metal hard mask overlying the gate structure. Optionally, the device has a second metal layer overlying the metal hard mask.
摘要:
A structure using pure silicon dioxide hard marsk for gate pattern. In an embodiment, the present invention provides a partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material in an etched source region and an etched drain region.