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1.
公开(公告)号:US10482964B2
公开(公告)日:2019-11-19
申请号:US16040837
申请日:2018-07-20
申请人: Da Woon Jeong , Sung-Hun Lee , Seokjung Yun , Hyunmog Park , JoongShik Shin , Young-Bae Yoon
发明人: Da Woon Jeong , Sung-Hun Lee , Seokjung Yun , Hyunmog Park , JoongShik Shin , Young-Bae Yoon
IPC分类号: G11C16/04 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L21/768 , G11C5/02 , G11C5/06 , H01L49/02
摘要: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.
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2.
公开(公告)号:US10049744B2
公开(公告)日:2018-08-14
申请号:US15383213
申请日:2016-12-19
申请人: Da Woon Jeong , Sung-Hun Lee , Seokjung Yun , Hyunmog Park , JoongShik Shin , Young-Bae Yoon
发明人: Da Woon Jeong , Sung-Hun Lee , Seokjung Yun , Hyunmog Park , JoongShik Shin , Young-Bae Yoon
IPC分类号: H01L29/788 , G11C16/04 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L21/768 , G11C5/02 , G11C5/06
摘要: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.
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