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    NON-VOLATILE MEMORY DEVICES INCLUDING SHARED BIT LINES AND METHODS OF FABRICATING THE SAME
    4.
    发明申请
    NON-VOLATILE MEMORY DEVICES INCLUDING SHARED BIT LINES AND METHODS OF FABRICATING THE SAME 有权
    包含共享位线的非易失性存储器件及其制造方法

    公开(公告)号：US20120276729A1

    公开(公告)日：2012-11-01

    申请号：US13545711

    申请日：2012-07-10

    申请人： Young-bae YOON ,  Jeong-dong Choe ,  Hee-soo Kang ,  Dong-hoon Jang ,  Ki-hyun Kim

    发明人： Young-bae YOON ,  Jeong-dong Choe ,  Hee-soo Kang ,  Dong-hoon Jang ,  Ki-hyun Kim

    IPC分类号： H01L21/28

    CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11548

    摘要： Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

    摘要翻译： 提供了非易失性存储器件及其制造方法，包括改进的位线和接触形成，其可以降低电阻和寄生电容，从而降低制造成本并提高器件性能。 非易失性存储器件可以包括衬底; 形成在所述基板上的多个场区域，所述场区域中的每一个包括均匀的第一场和经由桥区域被划分为两个子区域的第二场; 形成在所述基板上的有源区，并且被定义为具有通过所述场区域的串结构，其中至少两个串可经由所述桥接区域之一连接; 并且可以在场区域上形成多个共享位线，并且经由位线触点连接到有源区，其中位线接触可以是直接接触。

    Method of manufacturing semiconductor device having shared bit line structure
    10.
    发明授权
    Method of manufacturing semiconductor device having shared bit line structure 有权
    制造具有共享位线结构的半导体器件的方法

    公开(公告)号：US08486802B2

    公开(公告)日：2013-07-16

    申请号：US13236751

    申请日：2011-09-20

    申请人： Dong-hoon Jang ,  Young-bae Yoon ,  Hee-soo Kang ,  Young-seop Rah ,  Jeong-dong Choe

    发明人： Dong-hoon Jang ,  Young-bae Yoon ,  Hee-soo Kang ,  Young-seop Rah ,  Jeong-dong Choe

    IPC分类号： H01L21/762

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519

    摘要： A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.

    摘要翻译： 一种半导体器件，包括具有第一和第二有源区的衬底，所述第一和第二有源区设置在隔离结构的相对侧上;以及位线，其电耦合到所述隔离结构上的所述第一有源区 区域和第二有源区域，并且电耦合到直接接触第一和第二有源区域中的至少一个的有源桥接图案，其中接触插塞电耦合到第一有源区域和第二有源区域，以及底表面 所述有源桥模式位于所述第一和第二有源区的顶表面之下。