公开(公告)号：US20100278332A1

公开(公告)日：2010-11-04

申请号：US12834247

申请日：2010-07-12

申请人： Dai YAMAMOTO ,  Jun Yajima ,  Kouichi Itoh

发明人： Dai YAMAMOTO ,  Jun Yajima ,  Kouichi Itoh

IPC分类号： H04L9/28

CPC分类号： H04L9/0625 ,  H04L2209/122 ,  H04L2209/125 ,  H04L2209/20 ,  H04L2209/24

摘要： In a MISTY1 FI function, an exclusive OR to which a round key KIij2 is inputted is arranged between an exclusive OR arranged on a 9-bit critical path in a first MISTY structure and a zero-extend conversion connected to the branching point of a 7-bit right system data path. Then, a 9-bit round key KIij1 is truncate-converted to seven bits, the exclusive OR of the seven bits and the round key KIij1 is calculated by an exclusive OR and the calculation result is inputted to an exclusive OR arranged on the right system data path in the second stage MISTY structure.

摘要翻译： 在MISTY1FF功能中，输入循环密钥KIij2的异或被布置在第一MISTY结构中的9位关键路径上的异或或连接到7的分支点的零扩展转换 右边的系统数据路径。 然后，9位循环密钥KIij1被截断转换为7位，通过异或来计算七位和循环密钥KIij1的异或，并将计算结果输入到排列在右系统上的异或 数据路径在第二阶段MISTY结构。

公开(公告)号：US20100278340A1

公开(公告)日：2010-11-04

申请号：US12834252

申请日：2010-07-12

申请人： Jun YAJIMA ,  Dai YAMAMOTO ,  Kouichi ITOH

发明人： Jun YAJIMA ,  Dai YAMAMOTO ,  Kouichi ITOH

IPC分类号： H04K1/00

CPC分类号： H04L9/0625 ,  H04L2209/122 ,  H04L2209/24 ,  H04L2209/805

摘要： When processing a data conversion function of a MISTY structure, such as the FO function of MISTY1, the logical calculation result t3 of the exclusive OR 614 of the process result of the FI function 602 of the MISTY structure in the second stage and a logical calculation result t1 of an exclusive OR 612 of the MISTY structure in the first stage is not stored in a register. The logical calculation result t3 and the logical calculation result of respective exclusive OR 642 and 643 are subject to a direct exclusive OR with the respective exclusive OR 642 and 643.

摘要翻译： 当处理诸如MISTY1的FO功能的MISTY结构的数据转换功能时，第二级的MISTY结构的FI功能602的处理结果的异或614的逻辑计算结果t3和逻辑计算 第一级的MISTY结构的异或612的结果t1不存储在寄存器中。 逻辑运算结果t3和各异或642和643的逻辑计算结果与各自的异或642和643进行直接异或运算。

公开(公告)号：US20110075836A1

公开(公告)日：2011-03-31

申请号：US12891467

申请日：2010-09-27

申请人： Dai YAMAMOTO ,  Kouichi Itoh

发明人： Dai YAMAMOTO ,  Kouichi Itoh

IPC分类号： H04L9/28

CPC分类号： G06F7/725 ,  H04L9/003 ,  H04L9/3066

摘要： An apparatus includes a data storage to store a window table storing a table value with an index value mapped to the table value, the index value having same number of bits as a window width, the table value being a sum of a basic table value and a non-zero table correction value, the basic table value being obtained by multiplying a point G on an elliptic curve. An arithmetic processor generates the index value by reading from a scalar value at a bit position assigned to each bit of the window with the window being shifted, reads the table value from the window table according to the index value, and performs a doubling operation and an addition operation using the read table value. A corrector performs a correction on arithmetic results with a specific correction value responsive to the table correction value.

摘要翻译： 一种装置，包括：数据存储器，用于存储存储具有映射到表格值的索引值的表格值的窗口表，所述索引值具有与窗口宽度相同的位数，所述表格值是基本表格值和 非零表校正值，通过将点G乘以椭圆曲线获得的基本表值。 算术处理器通过从分配给窗口移位的窗口的每个位的位位置的标量值读取生成索引值，根据索引值从窗口表读取表格值，并执行加倍操作，并且 使用读表值的加法运算。 校正器根据表校正值对具有特定校正值的算术结果进行校正。

公开(公告)号：US20100183143A1

公开(公告)日：2010-07-22

申请号：US12612290

申请日：2009-11-04

申请人： Dai YAMAMOTO ,  Kouichi Itoh

发明人： Dai YAMAMOTO ,  Kouichi Itoh

IPC分类号： H04L9/28

CPC分类号： H04L9/0625 ,  H04L2209/122

摘要： A cryptographic processing apparatus for performing arithmetic operation on an FL function and an FL−1 function in a cryptographic process includes a first arithmetic gate is configured to receive a first input bit string and a first extended key bit string, a first XOR gate configured to receive an output of the first arithmetic gate and a second input bit string, a second arithmetic gate configured to receive an output of the first XOR gate and a second extended key bit string, a second XOR gate configured to receive an output of the second arithmetic gate and the first input bit string, a third arithmetic gate configured to receive an output of the second XOR gate and the first extended key bit string, and a third XOR gate configured to receive an output of the third arithmetic gate and an output of the first XOR gate.

摘要翻译： 一种用于在密码处理中对FL功能和FL-1功能进行算术运算的加密处理装置，包括：第一运算门，被配置为接收第一输入位串和第一扩展密钥位串，第一XOR门被配置为 接收第一算术门和第二输入比特串的输出，第二运算门，被配置为接收第一异或门和第二扩展密钥位串的输出;第二异或门，被配置为接收第二算术的输出 栅极和第一输入位串，第三运算门，被配置为接收第二异或门和第一扩展密钥位串的输出;以及第三异或门，被配置为接收第三运算门的输出， 第一个XOR门。