公开(公告)号：US07307308B2

公开(公告)日：2007-12-11

申请号：US10797296

申请日：2004-03-09

申请人： Dana Lee ,  Bomy Chen ,  Sohrab Kianian

发明人： Dana Lee ,  Bomy Chen ,  Sohrab Kianian

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

摘要： A buried bit line read/program non-volatile memory cell and array is capable of achieving high density. The cell and array is made in a semiconductor substrate which has a plurality of spaced apart trenches, with a planar surface between the trenches. Each trench has a side wall and a bottom wall. Each memory cell has a floating gate for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having two portions. One of the source/drain regions is in the bottom wall of the trench. The floating gate is in the trench and is is over a first portion of the channel and is spaced apart from the side wall of the trench. A gate electrode controls the conduction of the channel in the second portion, which is in the planar surface of the substrate. The other source/drain region is in the substrate in the planar surface of the substrate. An independently controllable control gate is also in the trench, insulated from the floating gate and is capacitively coupled thereto. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode or from the floating gate to the source/drain region at the bottom wall of the trench. The source, drain and control gates are all substantially parallel to one another, with the gate electrode substantially perpendicular to the source/drain/control gates. The source/drain lines are buried in the substrate, creating a virtual ground array.

摘要翻译： 掩埋位线读/程序非易失性存储单元和阵列能够实现高密度。 电池和阵列由具有多个间隔开的沟槽的半导体衬底制成，沟槽之间具有平坦表面。 每个沟槽都有一个侧壁和一个底壁。 每个存储单元具有用于存储其上的电荷的浮动栅极。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有两个部分。 源/漏区中的一个位于沟槽的底壁。 浮动栅极在沟槽中，并且在沟槽的第一部分之上并且与沟槽的侧壁间隔开。 栅电极控制在衬底的平面中的第二部分中的沟道的导通。 另一个源极/漏极区域位于衬底的平面表面中的衬底中。 独立可控的控制栅极也在沟槽中，与浮动栅极绝缘并且与其电容耦合。 通过热通道电子注入的电池程序，并且通过Fowler-Nordheim将电子从浮栅隧穿到栅电极或从浮栅到沟槽底壁处的源极/漏极区擦除。 源极，漏极和控制栅极都基本上彼此平行，栅电极基本上垂直于源极/漏极/控制栅极。 源极/漏极线被埋在衬底中，形成虚拟接地阵列。

公开(公告)号：US20070007581A1

公开(公告)日：2007-01-11

申请号：US11520993

申请日：2006-09-14

申请人： Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

发明人： Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7885

摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

摘要翻译： 存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。 源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。 导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。 擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。 一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。

公开(公告)号：US07547603B2

公开(公告)日：2009-06-16

申请号：US11520993

申请日：2006-09-14

申请人： Bomy Chen ,  Sohrab Kianian ,  Yaw Wen Hu

发明人： Bomy Chen ,  Sohrab Kianian ,  Yaw Wen Hu

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7885

摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

摘要翻译： 存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。 源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。 导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。 擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。 一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。

公开(公告)号：US07190018B2

公开(公告)日：2007-03-13

申请号：US10409407

申请日：2003-04-07

申请人： Bomy Chen ,  Sohrab Kianian ,  Jack Frayer

发明人： Bomy Chen ,  Sohrab Kianian ,  Jack Frayer

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  H01L27/115

摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. An independently controllable control gate is insulated from each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. The independently controllable control gates permit an array of such memory cells to operate in a NAND configuration.

摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 独立可控的控制栅极与源极/漏极区域中的每一个绝缘，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。 独立可控的控制门允许这种存储器单元的阵列在NAND配置中操作。

公开(公告)号：US07205198B2

公开(公告)日：2007-04-17

申请号：US11521162

申请日：2006-09-14

申请人： Bomy Chen ,  Sohrab Kianian ,  Jack Frayer

发明人： Bomy Chen ,  Sohrab Kianian ,  Jack Frayer

IPC分类号： H01L23/336 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  H01L27/115

摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. An independently controllable control gate is insulated from each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. The independently controllable control gates permit an array of such memory cells to operate in a NAND configuration.

摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 独立可控的控制栅极与源极/漏极区域中的每一个绝缘，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。 独立可控的控制门允许这种存储器单元的阵列在NAND配置中操作。

公开(公告)号：US20070020854A1

公开(公告)日：2007-01-25

申请号：US11521162

申请日：2006-09-14

申请人： Bomy Chen ,  Sohrab Kianian ,  Jack Frayer

发明人： Bomy Chen ,  Sohrab Kianian ,  Jack Frayer

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  H01L27/115

摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. An independently controllable control gate is insulated from each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. The independently controllable control gates permit an array of such memory cells to operate in a NAND configuration.

摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 独立可控的控制栅极与源极/漏极区域中的每一个绝缘，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。 独立可控的控制门允许这种存储器单元的阵列在NAND配置中操作。

公开(公告)号：US07129536B2

公开(公告)日：2006-10-31

申请号：US10934246

申请日：2004-09-02

申请人： Bomy Chen ,  Sohrab Kianian ,  Yaw Wen Hu

发明人： Bomy Chen ,  Sohrab Kianian ,  Yaw Wen Hu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7885

摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

公开(公告)号：US20060043459A1

公开(公告)日：2006-03-02

申请号：US10934246

申请日：2004-09-02

申请人： Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

发明人： Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7885

摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

公开(公告)号：US06861315B1

公开(公告)日：2005-03-01

申请号：US10641432

申请日：2003-08-14

申请人： Bomy Chen ,  Sohrab Kianian

发明人： Bomy Chen ,  Sohrab Kianian

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of making an array of bi-directional non-volatile memory cells in a substrate of a substantially single crystalline semiconductive material, where the material has a first conductivity type with the substrate having a substantially planar surface, comprises forming a plurality of spaced apart substantially parallel trenches in a first direction in the planar surface. Each of the trenches has a sidewall and a bottom. A region of a second conductivity type is formed in the bottom of each trench. A floating gate is formed in each trench insulated and spaced apart from the sidewall of the trench. The floating gate has a first end near the bottom and a second end furthest away from the bottom. A layer of tunneling oxide is formed about the second end of each floating gate. A layer of word region is formed on the layer of tunneling oxide. The layer of word region extends in a second direction substantially perpendicular to the first direction. The layer of word region is cut into a plurality of strips in the second direction to form a plurality of spaced apart word lines. Each strip is spaced apart from one another and substantially parallel to one another, and cuts through the floating gate in each of the trenches. Electrical connections are made to each of the region of second conductivity type and each of the plurality of spaced apart word lines.

摘要翻译： 一种制造基本上单晶半导体材料的衬底中的双向非易失性存储单元的阵列的方法，其中所述材料具有第一导电类型，所述衬底具有基本平坦的表面，包括形成多个间隔开的 在平面表面上沿第一方向大致平行的沟槽。 每个沟槽都有一个侧壁和一个底部。 在每个沟槽的底部形成第二导电类型的区域。 在每个沟槽中形成浮动栅极，其与沟槽的侧壁绝缘并间隔开。 浮动门具有靠近底部的第一端和离底部最远的第二端。 围绕每个浮动栅极的第二端形成隧穿氧化物层。 在隧道氧化物层上形成一个字区域层。 单词区域的层在基本上垂直于第一方向的第二方向上延伸。 字区域在第二方向被切成多个条带以形成多个间隔开的字线。 每个条带彼此间隔开并且基本上彼此平行，并且穿过每个沟槽中的浮动栅极。 对第二导电类型的区域和多个间隔开的字线中的每一个进行电连接。

公开(公告)号：US20050037576A1

公开(公告)日：2005-02-17

申请号：US10641432

申请日：2003-08-14

申请人： Bomy Chen ,  Sohrab Kianian

发明人： Bomy Chen ,  Sohrab Kianian

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of making an array of bi-directional non-volatile memory cells in a substrate of a substantially single crystalline semiconductive material, where the material has a first conductivity type with the substrate having a substantially planar surface, comprises forming a plurality of spaced apart substantially parallel trenches in a first direction in the planar surface. Each of the trenches has a sidewall and a bottom. A region of a second conductivity type is formed in the bottom of each trench. A floating gate is formed in each trench insulated and spaced apart from the sidewall of the trench. The floating gate has a first end near the bottom and a second end furthest away from the bottom. A layer of tunneling oxide is formed about the second end of each floating gate. A layer of word region is formed on the layer of tunneling oxide. The layer of word region extends in a second direction substantially perpendicular to the first direction. The layer of word region is cut into a plurality of strips in the second direction to form a plurality of spaced apart word lines. Each strip is spaced apart from one another and substantially parallel to one another, and cuts through the floating gate in each of the trenches. Electrical connections are made to each of the region of second conductivity type and each of the plurality of spaced apart word lines.

摘要翻译： 一种制造基本上单晶半导体材料的衬底中的双向非易失性存储单元的阵列的方法，其中所述材料具有第一导电类型，所述衬底具有基本平坦的表面，包括形成多个间隔开的 在平面表面上沿第一方向大致平行的沟槽。 每个沟槽都有一个侧壁和一个底部。 在每个沟槽的底部形成第二导电类型的区域。 在每个沟槽中形成浮动栅极，其与沟槽的侧壁绝缘并间隔开。 浮动门具有靠近底部的第一端和离底部最远的第二端。 围绕每个浮动栅极的第二端形成隧穿氧化物层。 在隧道氧化物层上形成一个字区域层。 单词区域的层在基本上垂直于第一方向的第二方向上延伸。 字区域在第二方向被切成多个条带以形成多个间隔开的字线。 每个条带彼此间隔开并且基本上彼此平行，并且穿过每个沟槽中的浮动栅极。 对第二导电类型的区域和多个间隔开的字线中的每一个进行电连接。