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1.发明授权MRAM with vertical storage element in two layer-arrangement and field sensor 失效MRAM具有垂直存储元件，在两层布置和场传感器中公开(公告)号：US07088612B2
公开(公告)日：2006-08-08
申请号：US10923639
申请日：2004-08-20
申请人： Daniel Braun , Peter Beer , Rainer Leuschner , Ulrich Klostermann
发明人： Daniel Braun , Peter Beer , Rainer Leuschner , Ulrich Klostermann
IPC分类号： G11C11/15
CPC分类号： G11C11/15
摘要： A magnetic memory element including a magnetic storage element including two magnetic layers made of magnetic material, said two magnetic layers opposing each other in a parallel relationship and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, said two magnetic layers further having a magnetic anisotropy, while its magnetization vectors are magnetically coupled to at least one current line, wherein said two magnetic layers are arranged on a same side of said at least one current line, and a magnetic sensor element including at least one magnetic layer having a magnetization vector being magnetically coupled to said magnetization vectors of said two magnetic layers of said magnetic storage element, said magnetic sensor element being electrically coupled to said at least one current line.
摘要翻译： 一种磁存储元件，包括由磁性材料制成的两个磁性层的磁存储元件，所述两个磁性层相对于彼此相对并且相对于其上形成有磁存储元件的晶片表面垂直取向，所述两个磁性层 进一步具有磁各向异性的层，而其磁化矢量磁耦合到至少一个电流线，其中所述两个磁性层布置在所述至少一条电流线的同一侧，以及包括至少一个磁性的磁性传感器元件 层，其磁化矢量磁耦合到所述磁存储元件的所述两个磁性层的所述磁化矢量，所述磁传感器元件电耦合到所述至少一条电流线。
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2.发明申请MRAM with vertical storage element in two layer-arrangement and field sensor 失效MRAM具有垂直存储元件，在两层布置和场传感器中公开(公告)号：US20060039186A1
公开(公告)日：2006-02-23
申请号：US10923639
申请日：2004-08-20
申请人： Daniel Braun , Peter Beer , Rainer Leuschner , Ulrich Klostermann
发明人： Daniel Braun , Peter Beer , Rainer Leuschner , Ulrich Klostermann
IPC分类号： G11C11/00
CPC分类号： G11C11/15
摘要： The present invention relates to a magnetic memory element comprising a magnetic storage element comprised of two magnetic layers made of magnetic material, said two magnetic layers opposing each other in a parallel relationship and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, said two magnetic layers further having a magnetic anisotropy, while its magnetization vectors are magnetically coupled to at least one current line, wherein said two magnetic layers are arranged on a same side of said at least one current line, and a magnetic sensor element comprising at least one magnetic layer having a magnetization vector being magnetically coupled to said magnetization vectors of said two magnetic layers of said magnetic storage element, said magnetic sensor element being electrically coupled to said at least one current line.
摘要翻译： 磁存储元件本发明涉及一种磁存储元件，它包括由磁性材料制成的两个磁性层构成的磁存储元件，所述两个磁性层相对于彼此相对并且相对于晶片表面垂直取向，在该晶片表面上磁性存储元件 所述两个磁性层进一步具有磁各向异性，而其磁化矢量磁耦合到至少一条电流线，其中所述两个磁性层布置在所述至少一条电流线的同一侧，并且磁传感器 元件包括至少一个磁性层，其磁化矢量磁耦合到所述磁存储元件的所述两个磁性层的所述磁化矢量，所述磁性传感器元件电耦合到所述至少一条电流线。
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公开(公告)号：US07092284B2
公开(公告)日：2006-08-15
申请号：US10922434
申请日：2004-08-20
IPC分类号： G11C11/14
CPC分类号： G11C11/15
摘要： A magnetic memory element is disclosed. The magnetic memory element includes a magnetic via for storing information, made of a magnetic material and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, the magnetic via having a magnetic anisotropy with its magnetization vector being magnetically coupled to at least one current line, and a magnetic sensor element comprising at least one magnetic layer having a magnetization vector being magnetically coupled to the magnetization vector of the magnetic via, wherein the magnetic sensor element being conductively connected to said at least one current line.
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公开(公告)号：US07075807B2
公开(公告)日：2006-07-11
申请号：US10920562
申请日：2004-08-18
IPC分类号： H01L29/82
CPC分类号： H01L27/222 , G11C11/16 , H01L43/08
摘要： A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.
摘要翻译： 磁阻或磁存储元件和具有一个或多个磁存储元件的磁随机存取存储器。 存储元件包括包含第一和第二磁性层的磁性隧道结。 第一磁性层具有自由磁化。 第一磁性层的自由磁化磁耦合到第一电流线和用于切换自由磁化的第二电流线，以及用于在第一和第二电流中的至少一个方向上施加静态磁偏移场的机构 线条。
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公开(公告)号：US20060039185A1
公开(公告)日：2006-02-23
申请号：US10922434
申请日：2004-08-20
IPC分类号： G11C11/00
CPC分类号： G11C11/15
摘要： A magnetic memory element is disclosed. The magnetic memory element includes a magnetic via for storing information, made of a magnetic material and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, the magnetic via having a magnetic anisotropy with its magnetization vector being magnetically coupled to at least one current line, and a magnetic sensor element comprising at least one magnetic layer having a magnetization vector being magnetically coupled to the magnetization vector of the magnetic via, wherein the magnetic sensor element being conductively connected to said at least one current line.
摘要翻译： 公开了一种磁存储元件。 磁存储元件包括用于存储由磁性材料制成并且相对于其上形成有磁存储元件的晶片表面垂直定向的磁通孔，磁通量具有磁各向异性，其磁化矢量磁耦合到 至少一个电流线，以及包括至少一个磁性层的磁性传感器元件，所述至少一个磁性层具有与磁通孔的磁化矢量磁耦合的磁化矢量，其中所述磁性传感器元件导电连接到所述至少一条电流线。
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公开(公告)号：US20060038211A1
公开(公告)日：2006-02-23
申请号：US10920562
申请日：2004-08-18
IPC分类号： H01L29/94
CPC分类号： H01L27/222 , G11C11/16 , H01L43/08
摘要： A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.
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7.发明授权Integrated circuits; method for manufacturing an integrated circuit; method for decreasing the influence of magnetic fields; memory module 失效集成电路; 集成电路制造方法; 降低磁场影响的方法; 内存模块公开(公告)号：US07697322B2
公开(公告)日：2010-04-13
申请号：US11775599
申请日：2007-07-10
IPC分类号： G11C11/00
CPC分类号： G11C11/15 , H01L27/222 , H01L43/08
摘要： Embodiments of the invention relate generally to integrated circuits, to a method for manufacturing an integrated circuit, to a method for decreasing the influence of magnetic fields, and to a memory module. In an embodiment of the invention, an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction may include a free layer with a magnetization orientation that is selected by the application of a write current through the magnetic tunnel junction, and a retention layer that retains the selectable magnetization orientation of the free layer at temperatures below a retention temperature.
摘要翻译： 本发明的实施例一般涉及集成电路，集成电路的制造方法，减小磁场影响的方法以及存储器模块。 在本发明的实施例中，提供了具有磁性隧道结的集成电路。 磁性隧道结可以包括具有通过施加通过磁性隧道结的写入电流而选择的磁化取向的自由层，以及在低于保持温度的温度下保持自由层的可选磁化取向的保留层。
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8.发明申请Integrated Circuit, Memory Cell Array, Memory Module, and Method of Operating an Integrated Circuit 有权集成电路，存储单元阵列，存储器模块和操作集成电路的方法公开(公告)号：US20090273966A1
公开(公告)日：2009-11-05
申请号：US12114466
申请日：2008-05-02
IPC分类号： G11C11/02
CPC分类号： G11C11/1675 , G11C11/1659
摘要： According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.
摘要翻译： 根据本发明的一个实施例，集成电路包括多个热可选择存储单元，每个存储单元连接到导电线，该导线具有用于施加加热电流的第一部分和用于施加加热电流的第二部分 编程电流。 集成电路被配置为使得加热电流和编程电流可以彼此独立地分别路由到导线的第一和第二部分。
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9.发明申请公开(公告)号：US20090016096A1
公开(公告)日：2009-01-15
申请号：US11775599
申请日：2007-07-10
CPC分类号： G11C11/15 , H01L27/222 , H01L43/08
摘要： Embodiments of the invention relate generally to integrated circuits, to a method for manufacturing an integrated circuit, to a method for decreasing the influence of magnetic fields, and to a memory module. In an embodiment of the invention, an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction may include a free layer with a magnetization orientation that is selected by the application of a write current through the magnetic tunnel junction, and a retention layer that retains the selectable magnetization orientation of the free layer at temperatures below a retention temperature.
摘要翻译： 本发明的实施例一般涉及集成电路，集成电路的制造方法，减小磁场影响的方法以及存储器模块。 在本发明的实施例中，提供了具有磁性隧道结的集成电路。 磁性隧道结可以包括具有通过施加通过磁性隧道结的写入电流而选择的磁化取向的自由层，以及在低于保持温度的温度下保持自由层的可选磁化取向的保留层。
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公开(公告)号：US08665629B2
公开(公告)日：2014-03-04
申请号：US11864575
申请日：2007-09-28
申请人： Human Park , Ulrich Klostermann , Rainer Leuschner
发明人： Human Park , Ulrich Klostermann , Rainer Leuschner
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , H01L27/2436 , H01L29/66795 , H01L29/785
摘要： An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.
摘要翻译： 对集成电路的集成电路及其制造方法进行说明。 在一个实施例中，集成电路包括包括电阻率变化存储元件的存储单元。 电阻率变化存储元件电耦合到选择晶体管，该选择晶体管包括在源极和漏极之间形成在衬底表面上方的源极，漏极和鳍状结构的FinFET。 翅片结构包括在基本上平行于衬底的表面的方向上延伸的沟道区，以及围绕沟道区的至少一部分形成的介电层，使得选择晶体管的有效沟道宽度至少部分依赖于 翅片结构的高度。
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