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公开(公告)号：US5949769A
公开(公告)日：1999-09-07
申请号：US541337
申请日：1995-10-10
申请人： Daniel Davidson , Ronald Duane McCallister , Robert Jeffrey Dahl , John Michael Liebetreu , Robert John Solem
发明人： Daniel Davidson , Ronald Duane McCallister , Robert Jeffrey Dahl , John Michael Liebetreu , Robert John Solem
CPC分类号： H04W28/22 , H04L5/1446 , H04L5/1453 , H04W56/0035 , H04W84/14 , H04W4/06 , H04W48/08 , H04W48/16 , H04W72/0446 , H04W74/04
摘要： A local multipoint data distribution system (10) simultaneously accommodates many communication sessions occurring at a wide variety of data rates. space surrounding cell sites (12) is partitioned into sectors (16), and the spectrum is allocated to the cell sites (12) so that adjacent sectors (16) use different spectrum portions, but the entire spectrum is reused numerous times at each cell site (12). A time diversity scheme allocates different numbers of time slots (54) to different calls. Time slot identifiers are assigned in contiguous blocks in an assigned numbering system (56). The time slot identifier assignments are translated into a counted numbering system (58) which causes the time slots (54) for any call to be distributed throughout a frame (48) and interleaved with time slots (54) assigned to other calls. Data communications use a common modulation format and a modulation order that is specifically adapted to a particular call, thus maintaining system capacity for any spatial distribution, quality requirement, and data requirement for subscriber units (14).
摘要翻译： 本地多点数据分发系统（10）同时容纳以各种数据速率发生的许多通信会话。 空间周围的小区站点（12）被划分成扇区（16），并且频谱被分配给小区站点（12），使得相邻扇区（16）使用不同的频谱部分，但是整个频谱在每个小区被重复使用多次 场地（12）。 时间分集方案将不同数量的时隙（54）分配给不同的呼叫。 在分配的编号系统（56）中的连续块中分配时隙标识符。 时隙标识符分配被转换成计数的编号系统（58），其使得任何呼叫的时隙（54）分布在整个帧（48）中并与分配给其他呼叫的时隙（54）进行交织。 数据通信使用专用于特定呼叫的公共调制格式和调制顺序，从而维持用于用户单元（14）的任何空间分布，质量要求和数据要求的系统容量。
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2.发明授权
公开(公告)号：US5774084A
公开(公告)日：1998-06-30
申请号：US627930
申请日：1996-04-03
摘要： A pulse width modulation (PWM) circuit translates digital data into an analog signal. The PWM circuit includes at least a digital counter, a significance reverser, and a comparator circuit. The significance reverser reverses the relative order of significance of at least two bits in the count words generated by the counter. The comparator determines whether the magnitude of a digital input word is greater than the magnitude of the reversed order count word. The PWM circuit produces a high output when the magnitude of the input word is greater than the magnitude of the reversed order count word and a low output when the magnitude of the input word is not greater than the magnitude of the reversed order count word. The analog output produced by the PWM circuit includes a number of pulses evenly distributed during the count cycle of the counter, and the input word indicates a duty cycle for the analog output. The PWM circuit includes a programmable output gain feature and an output interface that mimics the output configuration of conventional phase/frequency detector circuits.
摘要翻译： 脉冲宽度调制（PWM）电路将数字数据转换为模拟信号。 PWM电路至少包括一个数字计数器，一个有效反向器和一个比较器电路。 显着性反转器反转由计数器产生的计数字中至少两位的显着性的相对顺序。 比较器确定数字输入字的大小是否大于反转顺序计数字的大小。 当输入字的大小大于反相计数字的大小时，PWM电路产生高输出，而当输入字的大小不大于反转顺序计数字的大小时，PWM电路产生高输出。 由PWM电路产生的模拟输出包括在计数器的计数周期期间均匀分布的脉冲数，输入字表示模拟输出的占空比。 PWM电路包括可编程输出增益特征和模拟常规相位/频率检测器电路的输出配置的输出接口。
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公开(公告)号：US5721756A
公开(公告)日：1998-02-24
申请号：US620671
申请日：1996-03-26
摘要： A digital data receiver includes tunable analog components having variable parameters that are responsive to the bit error rate (BER) of the decoded digital data. The analog components include a quadrature generator having a tunable phase shifter, an analog filter having a tunable bandwidth, a tunable magnitude equalizer circuit, a tunable group delay equalizer circuit, and an amplifier having an adjustable gain. The tunable components are controlled by tuning control signals that incorporate digitally-produced fine tuning signals. The digital tuning signals are altered in accordance with realtime changes in the BER.
摘要翻译： 数字数据接收机包括具有可变参数的可调模拟分量，该参数响应于解码的数字数据的误码率（BER）。 模拟部件包括具有可调谐移相器的正交发生器，具有可调谐带宽的模拟滤波器，可调幅度均衡器电路，可调组延迟均衡器电路和具有可调节增益的放大器。 通过调谐控制信号控制可调组件，该控制信号包含数字产生的微调信号。 数字调谐信号根据BER的实时变化而改变。
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公开(公告)号：US5949832A
公开(公告)日：1999-09-07
申请号：US820084
申请日：1997-03-19
CPC分类号： H04L1/0059 , H04L1/0001 , H04L1/0054 , H04L1/203
摘要： A digital data receiver includes a tunable analog matched filter circuit having a variable bandwidth responsive to the bit error rate (BER) of the decoded data. The bandwidth of the analog filtering circuit is controlled by a tuning control signal that includes a coarse tuning signal combined with a fine tuning signal. The coarse tuning signal is generated by a frequency-to-current converter and the fine tuning signal is generated by a current-scaling digital-to-analog converter (DAC). The DAC input signal is produced by a DAC control circuit that includes a BER comparator and a DAC control state machine. The BER comparator determines whether the BER has improved or degraded in response to a previous tuning command. To optimize the BER in the decoded data signal, the state machine increments or decrements the value of the fine tuning signal, which in turn alters the filter bandwidth.
摘要翻译： 数字数据接收机包括具有响应于解码数据的误码率（BER）的可变带宽的可调谐模拟匹配滤波器电路。 模拟滤波电路的带宽由包括与微调信号组合的粗调谐信号的调谐控制信号控制。 粗调谐信号由频率 - 电流转换器产生，微调信号由电流比例数模转换器（DAC）产生。 DAC输入信号由包括BER比较器和DAC控制状态机的DAC控制电路产生。 BER比较器确定BER是否响应于先前的调谐命令而改善或降级。 为了优化解码数据信号中的BER，状态机递增或递减微调信号的值，从而改变滤波器带宽。
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