公开(公告)号：US5274738A

公开(公告)日：1993-12-28

申请号：US815202

申请日：1991-12-31

申请人： Daniel F. Daly ,  John J. Dwyer ,  Mark N. Harris ,  Salvatore J. Morlando ,  Thomas C. Grandy ,  Mark Sekas ,  Shamla V. Sharma ,  Jy-Hong Su

发明人： Daniel F. Daly ,  John J. Dwyer ,  Mark N. Harris ,  Salvatore J. Morlando ,  Thomas C. Grandy ,  Mark Sekas ,  Shamla V. Sharma ,  Jy-Hong Su

IPC分类号： H04M3/50 ,  G10L9/00

CPC分类号： H04M3/50

摘要： A digital voice processing system wherein voice processing functions are run in software. This application of software allows a modular structure because the application software resides in boards that are coupled to a host computer. With this structure, the software can be updated as required and the capacity of the system can be readily expanded to meet increased needs.

公开(公告)号：US5524261A

公开(公告)日：1996-06-04

申请号：US329795

申请日：1994-10-26

申请人： Daniel F. Daly ,  Thomas C. Grandy ,  Mark N. Harris ,  Salvatore J. Morlando ,  Mark Sekas ,  Shamla V. Sharma ,  John J. Dwyer

发明人： Daniel F. Daly ,  Thomas C. Grandy ,  Mark N. Harris ,  Salvatore J. Morlando ,  Mark Sekas ,  Shamla V. Sharma ,  John J. Dwyer

IPC分类号： G06F13/16 ,  G06F13/362 ,  G06F13/14

CPC分类号： G06F13/1605 ,  G06F13/362

摘要： An interface chip is capable of receiving requests from two processors and coordinating the flow of the data therebetween. The chip functions as a dual port controller for interaction of associated RAMs and processors of a voice processing system. A plurality of interfaces of the instant invention can be placed in communication with a host computer (PC) of a voice processing system that determines the priority of requests that are received from units of the system. The interface circuits are in communication with the host computer for the purpose of accepting requests in sequence and outputting data over a bus. The host computer is in communication with a RAM interface of each chip that interfaces local peripheral board processor through a dual port RAM which resides on the peripheral board. The interface chip contains the circuitry that creates communication with the resident RAM.

摘要翻译： 接口芯片能够接收来自两个处理器的请求并协调它们之间的数据流。 该芯片用作双端口控制器，用于语音处理系统的相关RAM和处理器的交互。 本发明的多个接口可以被放置为与确定从系统的单元接收的请求的优先级的语音处理系统的主机（PC）通信。 接口电路与主计算机通信，用于顺序接受请求并通过总线输出数据。 主机与每个芯片的RAM接口通信，该接口通过驻留在外设板上的双端口RAM接口本地外设板处理器。 接口芯片包含创建与驻留RAM通信的电路。

公开(公告)号：US5457782A

公开(公告)日：1995-10-10

申请号：US147421

申请日：1993-09-29

申请人： Daniel F. Daly ,  Thomas C. Grandy ,  Mark N. Harris ,  Salvatore J. Morlando ,  Mark Sekas ,  Shamla V. Sharma

发明人： Daniel F. Daly ,  Thomas C. Grandy ,  Mark N. Harris ,  Salvatore J. Morlando ,  Mark Sekas ,  Shamla V. Sharma

IPC分类号： H04M3/487 ,  H04M3/533 ,  G10L9/00

CPC分类号： H04M3/487 ,  H04M3/533

摘要： A digital voice processing circuit board having use in a voice processing system wherein voice processing functions are run in software. This application of software allows a modular structure since the application software resides in boards that are coupled to a host computer. With this structure, the software can be updated as required and the capacity of the system can be expanded readily to meet increased needs. The digital voice processing board has an interface chip to which random access memories are connected for temporary storage of data and storage of the operating code for the voice processing card. The interface is in communication with an application processor which runs the application programming and database management. The application processor is in communication with and controls a pair of signal processors which are in communication with a time division multiplexer chip which in turn is in communication with the bus. The signal processors perform digital signal processing such as decoding control information, telephone processing, compression and decompression, and tone generation.

摘要翻译： 一种在语音处理系统中使用的数字语音处理电路板，其中语音处理功能以软件运行。 软件的这种应用允许模块化结构，因为应用软件驻留在耦合到主计算机的板中。 通过这种结构，可以根据需要更新软件，并可以轻松扩展系统的容量以满足更多的需求。 数字语音处理板具有连接随机存取存储器的接口芯片，用于暂时存储数据并存储语音处理卡的操作码。 该接口与运行应用程序编程和数据库管理的应用程序处理器通信。 应用处理器与时分多路复用器芯片通信并控制一对信号处理器，该时分复用器芯片又与总线通信。 信号处理器执行诸如解码控制信息，电话处理，压缩和解压缩以及音调生成之类的数字信号处理。

公开(公告)号：US5404455A

公开(公告)日：1995-04-04

申请号：US816404

申请日：1991-12-31

申请人： Daniel F. Daly ,  John J. Dwyer ,  Salvatore J. Morlando ,  Mark Sekas ,  Shamla V. Sharma ,  Judith Dixon-Otton

发明人： Daniel F. Daly ,  John J. Dwyer ,  Salvatore J. Morlando ,  Mark Sekas ,  Shamla V. Sharma ,  Judith Dixon-Otton

IPC分类号： H04M3/487 ,  H04M3/533 ,  H04Q11/04 ,  G06F15/02

CPC分类号： H04Q11/0421 ,  H04M3/487 ,  H04M3/533

摘要： A time division multiplexer (TDM) chip having particular application in a digital voice processing system wherein voice processing functions are run in software. The TDM chip has a pair of RAMs which are in communication with a bus and at least one interface that provides communication with other devices. An bank switch controls the RAMs so that their communication with the bus and the interface alternates, i.e. while the first RAM is in communication with the interface the other RAM is in communication with the bus. After a determined period the communications are reversed. This scheme provides faster processing and more efficient use of the components. Including is a provision for allowing multiple interfaces to communicate with the RAM alternatively in a time shared manner.

摘要翻译： 一种在数字语音处理系统中具有特定应用的时分复用器（TDM）芯片，其中语音处理功能以软件运行。 TDM芯片具有与总线通信的一对RAM和提供与其他设备的通信的至少一个接口。 银行开关控制RAM，使得它们与总线和接口的通信交替，即当第一RAM与其他RAM与总线通信的接口通信时。 经过一段确定的期限后，通信被扭转。 该方案提供更快速的处理和更有效地使用组件。 包括是允许多个接口以时间共享方式与RAM交换的规定。