SYSTEM, METHOD, AND DEVICE FOR MACHINE
    1.
    发明申请
    SYSTEM, METHOD, AND DEVICE FOR MACHINE 审中-公开
    系统,方法和机器设备

    公开(公告)号:US20120296450A1

    公开(公告)日:2012-11-22

    申请号:US13110859

    申请日:2011-05-18

    IPC分类号: G05B9/02 H01B9/00

    摘要: Embodiments of the invention provide systems, methods, and devices for controlling a machine. In one embodiment, the invention provides a system for a machine, the system comprising: a device including: a module adapted to perform a support function associated with a machine; and a power cable for connecting the module to an electrical supply, the power cable including an identifier operable to be read by the device; and a host computer operable to: receive from the device a request for a network identifier for the device, the request including information from the identifier; and obtain the network identifier using the information from the identifier.

    摘要翻译: 本发明的实施例提供了用于控制机器的系统,方法和装置。 在一个实施例中,本发明提供了一种用于机器的系统,所述系统包括:设备,包括:适于执行与机器相关联的支持功能的模块; 以及用于将模块连接到电源的电力电缆,所述电力电缆包括可操作以由所述装置读取的标识符; 以及主计算机,可操作用于:从所述设备接收对所述设备的网络标识符的请求,所述请求包括来自所述标识符的信息; 并使用来自标识符的信息获取网络标识符。

    SYSTEMS AND METHODS FOR PROVIDING TIME SYNCHRONIZATION
    2.
    发明申请
    SYSTEMS AND METHODS FOR PROVIDING TIME SYNCHRONIZATION 审中-公开
    提供时间同步的系统和方法

    公开(公告)号:US20110222561A1

    公开(公告)日:2011-09-15

    申请号:US12721904

    申请日:2010-03-11

    IPC分类号: H04J3/06

    摘要: Systems and methods for providing time synchronization in a local network are provided. A time source may be configured to determine a current time and a designated time at which a reference signal will be output, and to output the reference signal when the designated time is reached. A network host communicatively coupled to the time source may be configured to (i) identify the designated time and (ii) communicate the identified designated time to one or more network devices via a local network. The one or more network devices may be respectively configured to (i) initiate an internal clock, (ii) receive the designated time from the network host, (iii) receive the reference signal output be the time source subsequent to receiving the designated time, and (iv) set a value of the internal clock to the designated time upon receipt of the reference signal.

    摘要翻译: 提供了用于在本地网络中提供时间同步的系统和方法。 时间源可以被配置为确定当前时间和将被输出参考信号的指定时间,并且在达到指定时间时输出参考信号。 可通信地耦合到时间源的网络主机可以被配置为(i)识别指定的时间,并且(ii)经由本地网络将所识别的指定时间传送到一个或多个网络设备。 一个或多个网络设备可以分别被配置为(i)启动内部时钟,(ii)从网络主机接收指定的时间,(iii)接收作为接收指定时间之后的时间源的参考信号输出, 和(iv)在接收到参考信号时将内部时钟的值设置到指定的时间。

    Systems and methods for concatenating multiple devices
    3.
    发明授权
    Systems and methods for concatenating multiple devices 有权
    用于连接多个设备的系统和方法

    公开(公告)号:US08943250B2

    公开(公告)日:2015-01-27

    申请号:US13589839

    申请日:2012-08-20

    IPC分类号: G06F13/00

    CPC分类号: G06F13/4291 G06F13/4247

    摘要: System and methods are provided. In one embodiment, a system includes serial peripheral interface (SPI) bus and a master device communicatively coupled to the serial peripheral interface (SPI) bus. The system further includes a first slave device communicatively coupled to the SPI bus. The system additionally includes a second slave device communicatively coupled to the SPI bus and to the first slave device; wherein the first and the second slave devices are communicatively coupled in parallel to the SPI bus and wherein the first and the second slave devices are communicatively coupled to each other by using a first chain line, and wherein the master device is configured to communicate with the first and with the second slave devices over the SPI bus.

    摘要翻译: 提供了系统和方法。 在一个实施例中,系统包括串行外围接口(SPI)总线和通信地耦合到串行外设接口(SPI)总线的主设备。 该系统还包括通信地耦合到SPI总线的第一从设备。 该系统还包括通信地耦合到SPI总线和第一从设备的第二从设备; 其中所述第一和第二从属设备与所述SPI总线并行地通信耦合,并且其中所述第一和第二从设备通过使用第一链路通信地彼此耦合,并且其中所述主设备被配置为与 首先通过SPI总线与第二个从器件连接。

    CONFIGURABLE ANALOG INPUT CHANNEL WITH GALVANIC ISOLATION
    4.
    发明申请
    CONFIGURABLE ANALOG INPUT CHANNEL WITH GALVANIC ISOLATION 有权
    可配置模拟输入通道与隔离隔离

    公开(公告)号:US20110227773A1

    公开(公告)日:2011-09-22

    申请号:US12726763

    申请日:2010-03-18

    IPC分类号: H03M1/12

    CPC分类号: H03M3/392 H03M3/368 H03M3/458

    摘要: Embodiments of the invention relate generally to a configurable analog input channel with galvanic isolation. In one embodiment, the invention provides a configurable input channel for selectively receiving one of a plurality of different analog sensor inputs. The input channel includes an interface for implementing switch settings for a selected type of input signal; a set of input terminals, wherein at least two of the set of input terminals are selectively utilized to correspond with the selected type of input signal; an analog-to-digital converter for converting the input signal into a digital output, wherein an operation of the analog-to-digital converter is determined based on the switch settings; and an isolation barrier for isolating the configurable input channel.

    摘要翻译: 本发明的实施例一般涉及具有电隔离的可配置模拟输入通道。 在一个实施例中,本发明提供了一种用于选择性地接收多个不同模拟传感器输入中的一个的可配置输入通道。 输入通道包括用于实现所选类型的输入信号的开关设置的接口; 一组输入端子,其中所述一组输入端子中的至少两个选择性地用于与所选择的输入信号类型对应; 用于将输入信号转换为数字输出的模拟 - 数字转换器,其中基于开关设置确定模数转换器的操作; 以及用于隔离可配置输入通道的隔离屏障。

    Systems and Methods for Programmatically Filtering Frequency Signals
    5.
    发明申请
    Systems and Methods for Programmatically Filtering Frequency Signals 有权
    用于编程过滤频率信号的系统和方法

    公开(公告)号:US20140029632A1

    公开(公告)日:2014-01-30

    申请号:US13557957

    申请日:2012-07-25

    IPC分类号: H04J1/00

    摘要: Certain embodiments herein describe filtering signals or channels using a programmable bandwidth filter. Each channel may be filtered according to a different bandwidth such that noise may be removed from each channel without the need to increase the complexity of an anti-aliasing filter, for example. In one embodiment, the programmable filter may be a decimation filter that may be coupled to a delta sigma modulator, which may sample an analog channel according to a programmable sampling rate to generate a digital representation of the analog channel. In one embodiment, multiple analog channels may be multiplexed and subsequently sampled and filtered by the delta sigma modulator and decimation filter, respectively. According to various embodiments, the above processing may be performed by an application specific integrated circuit (ASIC), a microcontroller, or a computing device including one or more software programs and/or modules.

    摘要翻译: 本文中的某些实施例描述了使用可编程带宽滤波器来滤波信号或信道。 可以根据不同的带宽对每个信道进行滤波,以便例如可以从每个信道去除噪声,而不需要增加抗混叠滤波器的复杂度。 在一个实施例中,可编程滤波器可以是可以耦合到Δ-Σ调制器的抽取滤波器,其可以根据可编程采样率对模拟信道采样以产生模拟信道的数字表示。 在一个实施例中,多个模拟通道可以被多路复用并随后由ΔΣ调制器和抽取滤波器进行采样和滤波。 根据各种实施例,上述处理可以由专用集成电路(ASIC),微控制器或包括一个或多个软件程序和/或模块的计算设备执行。

    Systems and Methods for Determining Electrical Ground Faults
    6.
    发明申请
    Systems and Methods for Determining Electrical Ground Faults 有权
    确定电接地故障的系统和方法

    公开(公告)号:US20120299598A1

    公开(公告)日:2012-11-29

    申请号:US13180103

    申请日:2011-07-11

    IPC分类号: G01R31/14

    CPC分类号: G01R31/025

    摘要: Certain embodiments of the invention may include systems and methods for determining electrical ground faults. According to an example embodiment of the invention, a method is provided determining ground leakage electrical faults. The method includes providing a voltage source having a positive lead in communication with a first contact conductor and a negative lead in communication with a second field conductor, wherein the first contact conductor is connected to a ground through a first resistor Rp, and wherein the second field conductor is connected to the ground through a second resistor Rn; monitoring a first voltage potential associated with the first contact conductor; and determining a condition associated with the first contact conductor, based at least in part on the monitored first voltage potential.

    摘要翻译: 本发明的某些实施例可以包括用于确定电接地故障的系统和方法。 根据本发明的示例性实施例,提供了一种确定接地漏电电故障的方法。 该方法包括提供具有与第一接触导体连通的正引线的电压源和与第二场导体连通的负引线,其中第一接触导体通过第一电阻器Rp连接到地,并且其中第二 场导体通过第二电阻器Rn连接到地; 监测与所述第一接触导体相关联的第一电压电位; 以及至少部分地基于所监视的第一电压电位来确定与所述第一接触导体相关联的状态。

    HART CHANNEL INTERFACE COMPONENT INCLUDING REDUNDANCY
    7.
    发明申请
    HART CHANNEL INTERFACE COMPONENT INCLUDING REDUNDANCY 审中-公开
    HART频道界面组件,包括冗余

    公开(公告)号:US20120253481A1

    公开(公告)日:2012-10-04

    申请号:US13074781

    申请日:2011-03-29

    IPC分类号: G05B9/03

    摘要: A channel interface component including redundancy within a control system with highway addressable remote transfer (HART) channels is provided. In one embodiment, a circuit includes: at least two highway addressable remote transfer (HART) channels, each HART channel including an input terminal and an output terminal configured to connect with a HART device via a current loop; an channel interface component coupled to each HART channel that is configured to support HART protocol signals for communications with the HART device, wherein the channel interface component includes a suicide relay switch for connecting or disconnecting each HART channel from the HART device; and a programmable logic device coupled to the channel interface component that is configured to perform modulation and demodulation of HART protocol signals for communications with the HART device.

    摘要翻译: 提供了包括具有公路可寻址远程传输(HART)信道的控制系统内的冗余的信道接口组件。 在一个实施例中,电路包括:至少两个高速公路可寻址远程传输(HART)信道,每个HART信道包括输入端和被配置为经由电流环与HART设备连接的输出端; 耦合到每个HART信道的信道接口组件,其被配置为支持用于与HART设备通信的HART协议信号,其中所述信道接口组件包括用于从HART设备连接或断开每个HART信道的硅化物继电器开关; 以及耦合到所述信道接口部件的可编程逻辑器件,所述可编程逻辑器件被配置为执行用于与所述HART器件通信的HART协议信号的调制和解调。

    Isolated HART interface with programmable data flow
    8.
    发明授权
    Isolated HART interface with programmable data flow 有权
    具有可编程数据流的隔离HART接口

    公开(公告)号:US08073991B2

    公开(公告)日:2011-12-06

    申请号:US12687485

    申请日:2010-01-14

    IPC分类号: G06F13/00 G06F3/00

    摘要: An isolated highway addressable remote transfer (HART) interface with programmable data flow is provided. The isolated HART interface includes a HART channel having at least one pair of terminals configured to connect with a HART device via a current loop. The HART channel is programmable to have each pair of terminals assigned as a current loop input or a current loop output.

    摘要翻译: 提供了具有可编程数据流的隔离高速公路可寻址远程传输(HART)接口。 隔离的HART接口包括HART通道,其具有被配置为经由电流回路与HART设备连接的至少一对终端。 HART通道可编程为将每对端子分配为电流回路输入或电流回路输出。

    SYSTEMS AND METHODS FOR IMPROVED LINKING OF MASTER AND SLAVE DEVICES
    9.
    发明申请
    SYSTEMS AND METHODS FOR IMPROVED LINKING OF MASTER AND SLAVE DEVICES 有权
    用于改进主和从设备连接的系统和方法

    公开(公告)号:US20140075072A1

    公开(公告)日:2014-03-13

    申请号:US13615360

    申请日:2012-09-13

    IPC分类号: G06F13/36

    CPC分类号: G06F13/4291 G06F15/17

    摘要: System and methods are provided. In one embodiment, a system includes a master device comprising a first serial peripheral interface (SPI) port having only a first four wires. The system further includes a slave device comprising a second SPI port having only a second four wires. The system additionally includes a galvanic isolation barrier communicatively coupling the first four wires to the second four wires. The master device is configured to use the first four wires to transmit a plurality of signals representative of a reset and of a first communications mode. The first communications mode is used to transfer data between the master device and the slave device.

    摘要翻译: 提供了系统和方法。 在一个实施例中,系统包括主设备,该主设备包括仅具有前四条线的第一串行外设接口(SPI)端口。 该系统还包括从设备,其包括仅具有第二四条电线的第二SPI端口。 该系统还包括通过电连接将前四条电线耦合到第二四条电线的电隔离屏障。 主设备被配置为使用前四条线来发送表示复位和第一通信模式的多个信号。 第一种通信模式用于在主设备和从设备之间传输数据。

    Configurable analog input circuit
    10.
    发明授权
    Configurable analog input circuit 有权
    可配置的模拟输入电路

    公开(公告)号:US08373586B2

    公开(公告)日:2013-02-12

    申请号:US12942643

    申请日:2010-11-09

    IPC分类号: H03M1/12

    CPC分类号: H03M1/1225 H03M1/124

    摘要: Configurable analog input circuits are provided. An analog input circuit may include a plurality of configurable input channels, at least one analog-to-digital converter, and at least one processor. Each input channel may include a plurality of switches utilized to select a type of input signal received via the input channel and a set of input terminals selectively utilized to correspond with the selected type of input signal. The at least one analog-to-digital converter may be configured to convert, for each of the plurality of input channels, the selected type of input signal into a digital output. The at least one processor may be configured to control operation of the plurality of switches associated with each of the plurality of configurable input channels.

    摘要翻译: 提供可配置的模拟输入电路。 模拟输入电路可以包括多个可配置的输入通道,至少一个模拟 - 数字转换器和至少一个处理器。 每个输入通道可以包括多个开关,用于选择经由输入通道接收的输入信号的类型和一组选择性地用于与所选择的输入信号对应的输入端。 所述至少一个模拟 - 数字转换器可以被配置为将所选择的类型的输入信号转换成数字输出,对于多个输入通道中的每一个。 至少一个处理器可以被配置为控制与多个可配置输入通道中的每一个相关联的多个开关的操作。