公开(公告)号：US12021541B2

公开(公告)日：2024-06-25

申请号：US18129527

申请日：2023-03-31

Applicant: SIGMASENSE, LLC.

Inventor： Phuong Huynh

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12 ,  H03M1/34 ,  H03M3/00

CPC classification number: H03M1/004 ,  H03M1/0626 ,  H03M1/0854 ,  H03M1/1245 ,  H03M1/34 ,  H03M3/462 ,  H03M3/476 ,  H03M3/422

Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

公开(公告)号：US20240187019A1

公开(公告)日：2024-06-06

申请号：US18494541

申请日：2023-10-25

Applicant: Beyond Semiconductor, d.o.o.

Inventor： Matjaz Breskvar ,  Drago Strle

IPC: H03M3/00

CPC classification number: H03M3/462 ,  H03M3/422

Abstract: Systems and methods provide architectures for various applications, for example, for software defined radios and other high frequency (HF) application. Embodiments can provide novel multi path ΣΔ architectures that form the basis for novel N path Sigma Delta (NΣΔ) modulators, NΣΔ digital to analog converters (NΣΔ DAC) and NΣΔ analog to digital converters (NΣΔ ADC).

公开(公告)号：US11984902B2

公开(公告)日：2024-05-14

申请号：US18201896

申请日：2023-05-25

Applicant: SIGMASENSE, LLC.

Inventor： Grant Howard McGibney ,  Patrick Troy Gray ,  Gerald Dale Morrison ,  Daniel Keith Van Ostrand

IPC: H03M1/06 ,  G06F3/041 ,  G06F3/044 ,  H03H7/01 ,  H03M1/12 ,  H03M3/00

CPC classification number: H03M1/0626 ,  G06F3/044 ,  H03H7/0161 ,  H03M1/1245 ,  H03M3/462 ,  G06F3/041

Abstract: A digital decimation filtering circuit of an analog to digital conversion circuit includes an n-tap anti-aliasing filter operable to receive a 1-bit analog to digital converter (ADC) output signal at an oversampling rate and filter the 1-bit ADC output signal to remove frequencies higher than a selected cut-off frequency to produce an n-bit filtered signal at a first data output rate. The digital decimation filtering circuit further includes a decimator operable to receive the n-bit filtered signal at the first data output rate, decimate the n-bit filtered signal by a decimation factor to produce a set of output signals, and sum the set of outputs to produce a decimated signal at a second data output rate. The first data output rate is greater than the second data output rate.

公开(公告)号：US20240007128A1

公开(公告)日：2024-01-04

申请号：US18467501

申请日：2023-09-14

Applicant: Nuvoton Technology Corporation Japan

Inventor： Hitoshi KOBAYASHI

IPC: H03M3/00

CPC classification number: H03M3/462 ,  H03M3/48

Abstract: An analog-to-digital conversion circuit includes: a variable gain amplifier; a delta-sigma modulator that modulates an output of the variable gain amplifier to a pulse density modulation (PDM) signal; and a decimation filter that downsamples the PDM signal to output a first digital signal that is converted into a multi-bit digital signal. The decimation filter includes: a weight change unit that converts the PDM signal into a second digital signal that is weighted by multiplying a weight of the PDM signal by a reciprocal of an amplification factor of the variable gain amplifier; and a first digital filter that receives the second digital signal as an input, and outputs the first digital signal.

公开(公告)号：US20190252976A1

公开(公告)日：2019-08-15

申请号：US16117402

申请日：2018-08-30

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： ShinHye Chun ,  Hyung Bin Ihm

IPC: H02M3/157 ,  H03M3/00 ,  H03H17/06

CPC classification number: H02M3/157 ,  H02M3/335 ,  H03M3/43 ,  H03M3/462

Abstract: A power conversion apparatus can include: a power module configured to transfer an analog sensing signal corresponding to a current of an inductor and a voltage applied at both terminals of a capacitor, and to perform power conversion by driving a power semiconductor with a pulse-width modulation signal; and a controller configured to receive the analog sensing signal from the power module, to convert the analog sensing signal to a digital signal, to generate the pulse-width modulation signal, and to transfer the pulse-width modulation signal to the power module.

公开(公告)号：US09973171B2

公开(公告)日：2018-05-15

申请号：US15316807

申请日：2015-05-15

Applicant: Azbil Corporation

Inventor： Tetsuya Kajita

IPC: H03H17/02 ,  H03M3/02

CPC classification number: H03H17/025 ,  H03H17/0282 ,  H03H17/0286 ,  H03H17/0671 ,  H03M3/02 ,  H03M3/462

Abstract: A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency fS that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency fS to reduce the sampling frequency fS to a sampling frequency fD=fS/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency fD and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples.

公开(公告)号：US20180129344A1

公开(公告)日：2018-05-10

申请号：US15864806

申请日：2018-01-08

Applicant: SYNAPTICS INCORPORATED

Inventor： Kirk HARGREAVES ,  Joseph Kurth REYNOLDS

IPC: G06F3/041 ,  H03M3/00

CPC classification number: G06F3/0416 ,  H03M3/462

Abstract: A processing system that includes a sigma-delta converter and a filter unit that applies a matched filter to the output of the sigma-delta converter. The processing system drives sensor electrodes for capacitive sensing and receives resulting signals with the sensor electrodes in response. The processing system applies these resulting signals to sigma-delta converters. The matched filter boosts the signal-to-noise ratio of the signal received from the sigma-delta converter, thereby improving the ability to sense presence of an input object. The filter unit may apply different, customized matched filters for different capacitive pixels to improve the signal-to-noise ratio of each capacitive pixel in a customized manner.

公开(公告)号：US20180123610A1

公开(公告)日：2018-05-03

申请号：US15174329

申请日：2016-06-06

Applicant: SEW-EURODRIVE GMBH & CO. KG

Inventor： Thomas Knapp ,  Hans Juergen Kollar ,  Wolfgang Hammel ,  Ulrich Neumayer

IPC: H03M3/00

CPC classification number: H03M3/462 ,  H03M1/645

Abstract: A method for processing a measured-value signal representing a value, determined in analog form, for the output current of a converter, and device for carrying out the method, the measured-value signals acquired by a sensor, especially including a shunt resistor, being supplied to a respective processing channel that has at least one delta-sigma modulator.

公开(公告)号：US20180034470A1

公开(公告)日：2018-02-01

申请号：US15225745

申请日：2016-08-01

Applicant: KOPIN CORPORATION

Inventor： Dashen Fan ,  Joseph Yong Kwon

IPC: H03M1/12 ,  H04B7/06

CPC classification number: H03M1/1245 ,  H03M3/462 ,  H04B7/0617

Abstract: Systems and methods are described to time delay a signal output from an analog-to-digital converter (ADC) The ADC includes a digital sensor responsive to an analog field quantity The digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency. A time delay element is configured to receive as an input the oversampled digital output signal and to output a time delayed oversampled digital output signal. A filter is configured to receive as an input the delayed oversampled digital output signal. The fitter low pass filters and decimates tea lower sample rate the delayed oversampled digital output signal. An output includes a low pass filtered decimated delayed digital output signal, where the lower sample rate is less than the sampling clock frequency.

公开(公告)号：US09864455B2

公开(公告)日：2018-01-09

申请号：US14726273

申请日：2015-05-29

Applicant: SYNAPTICS INCORPORATED

Inventor： Kirk Hargreaves ,  Joseph Kurth Reynolds

IPC: G06F3/044 ,  G06F3/041 ,  H03M3/00

CPC classification number: G06F3/0416 ,  H03M3/462

Abstract: A processing system that includes a sigma-delta converter and a filter unit that applies a matched filter to the output of the sigma-delta converter. The processing system drives sensor electrodes for capacitive sensing and receives resulting signals with the sensor electrodes in response. The processing system applies these resulting signals to sigma-delta converters. The matched filter boosts the signal-to-noise ratio of the signal received from the sigma-delta converter, thereby improving the ability to sense presence of an input object. The filter unit may apply different, customized matched filters for different capacitive pixels to improve the signal-to-noise ratio of each capacitive pixel in a customized manner.