公开(公告)号：US4472771A

公开(公告)日：1984-09-18

申请号：US206538

申请日：1980-11-13

申请人： Jacques M. J. Bienvenu ,  Pierre G. Antoine ,  Robert J. A. Bavoux ,  Daniel R. Vinot

发明人： Jacques M. J. Bienvenu ,  Pierre G. Antoine ,  Robert J. A. Bavoux ,  Daniel R. Vinot

IPC分类号： G06F9/46 ,  G06F9/00 ,  G06F13/18 ,  G06F15/16

CPC分类号： G06F13/18

摘要： A central sub-system of a data processing system, including an operator console controlling a service processor, is divided into several sub-units, functioning separately from each other. The sub-units include processors that are connected together and to a common controller for a common memory unit by data, address and control buses. Each sub-unit includes a configuration device that stores an appurtenance indicator derived from the service processor in response to sub-unit initialization, and enables its associated sub-unit to exchange data with the memory unit. The sub-unit having the highest priority of the sub-units attempting to access the memory units is connected to the memory unit by the controller. A single configuration memory stores an indication of the sub-units in service in the central sub-system. The configuration memory is addressed each time the memory unit is addressed by a signal indicative of the appurtenance indicator derived from the selected sub-unit. The configuration memory derives an authorization signal that commands performance of memory cycles by the selected unit when the configuration memory contains an indication that the selected sub-unit is in service in the sub-system. The controller includes memorization means for storing the highest priority sub-unit trying to access the memory unit. The memorization means derives an output that is coupled to the data address and control buses to transmit a signal indicative of the number of the sub-unit with data to be exchanged with the memory unit to each of the authorizing means, thereby to establish data transmission between the sub-unit having the highest priority and the memory unit.

摘要翻译： 数据处理系统的中央子系统，包括控制服务处理器的操作员控制台，被分成几个分开的子单元。 子单元包括通过数据，地址和控制总线连接在一起的处理器和用于公共存储器单元的公共控制器。 每个子单元包括配置设备，其存储响应于子单元初始化从服务处理器导出的应用指示符，并使其相关联的子单元与存储器单元交换数据。 尝试访问存储单元的子单元具有最高优先级的子单元通过控制器连接到存储器单元。 单个配置存储器将服务中的子单元的指示存储在中央子系统中。 每当存储器单元通过指示从所选择的子单元导出的附件指示符的信号寻址时寻址配置存储器。 当配置存储器包含所选择的子单元在子系统中服务的指示时，配置存储器导出授权信号，该授权信号命令所选单元执行存储器周期的性能。 控制器包括用于存储尝试访问存储器单元的最高优先级子单元的存储装置。 存储装置导出与数据地址和控制总线耦合的输出，以将表示具有与存储器单元交换的数据的子单元的数量的信号发送到每个授权装置，从而建立数据传输 具有最高优先级的子单元与存储单元之间。

公开(公告)号：US4433375A

公开(公告)日：1984-02-21

申请号：US210359

申请日：1980-11-25

申请人： Daniel R. Vinot

发明人： Daniel R. Vinot

IPC分类号： G06F9/46 ,  G06F13/362 ,  G06F13/378 ,  G06F13/42 ,  G06F15/16 ,  G06F15/177 ,  G06F7/00

CPC分类号： G06F13/378 ,  G06F13/4217

摘要： A control logic circuit (C) is provided in each unit such as processors and memories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQ.sub.i L) of the unit itself and at the other input receives external calls (RQ.sub.k) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission bus only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.

摘要翻译： 在多处理器数据处理系统中的每个单元中提供控制逻辑电路（C），例如处理器和存储器。 每个控制逻辑电路（C）配备有一个优先级电路（P12），在一个输入端接收单元本身的合格本地呼叫（RQiL），另一个输入接收由其他单元发送的外部呼叫（RQk）。 控制逻辑电路（C）能够通过其传输单元进行控制，但只有当其优先级电路（P12）将该单元识别为具有最高优先级的其他单元时才能进行控制。 逻辑电路（C）与T电路（13）一起根据传输总线的数据线的占用状态选择本地呼叫。

公开(公告)号：US4611276A

公开(公告)日：1986-09-09

申请号：US591237

申请日：1984-03-20

申请人： Daniel R. Vinot

发明人： Daniel R. Vinot

IPC分类号： G06F9/46 ,  G06F13/362 ,  G06F13/378 ,  G06F13/42 ,  G06F15/16 ,  G06F15/177 ,  G06F13/36

CPC分类号： G06F13/378 ,  G06F13/4217

摘要： A control logic circuit (C) is provided in each unit such as processors andemories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQ.sub.i L) of the unit itself and at the other input receives external calls (RQ.sub.k) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission but only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.