公开(公告)号：US08665005B2

公开(公告)日：2014-03-04

申请号：US13310541

申请日：2011-12-02

申请人： Danilo Gerna ,  Enrico Sacchi

发明人： Danilo Gerna ,  Enrico Sacchi

IPC分类号： G05F1/10

CPC分类号： H03K3/011 ,  G05F3/245 ,  H02M3/156 ,  H03K3/012 ,  H03K3/013

摘要： The transition frequency of an inverter can vary with the transconductance of its internal transistors as a function of temperature and bias level. To maintain consistent transition frequency across temperatures, and therefore reduce the phase noise variation introduced by the inverter, systems, methods, and circuits are disclosed for biasing the inverter with a temperature varying current such that the transconductance of transistors remains constant across temperatures, while maintaining the lowest possible power consumption to do so. Various embodiments can include using current sources that have proportional-to-absolute-temperature (PTAT) devices.

摘要翻译： 逆变器的转换频率随其内部晶体管的跨导而变化，作为温度和偏置电平的函数。 为了保持恒定的跨越温度的转换频率，并且因此降低由逆变器引入的相位噪声变化，系统，方法和电路被公开用于使温度变化电流偏置逆变器，使得晶体管的跨导在温度保持恒定的同时保持 这样做最低的功耗。 各种实施例可以包括使用具有比例绝对温度（PTAT）装置的电流源。

公开(公告)号：US20120139617A1

公开(公告)日：2012-06-07

申请号：US13310541

申请日：2011-12-02

申请人： Danilo Gerna ,  Enrico Sacchi

发明人： Danilo Gerna ,  Enrico Sacchi

IPC分类号： H03K19/003

CPC分类号： H03K3/011 ,  G05F3/245 ,  H02M3/156 ,  H03K3/012 ,  H03K3/013

摘要： The transition frequency of an inverter can vary with the transconductance of its internal transistors as a function of temperature and bias level. To maintain consistent transition frequency across temperatures, and therefore reduce the phase noise variation introduced by the inverter, systems, methods, and circuits are disclosed for biasing the inverter with a temperature varying current such that the transconductance of transistors remains constant across temperatures, while maintaining the lowest possible power consumption to do so. Various embodiments can include using current sources that have proportional-to-absolute-temperature (PTAT) devices.

摘要翻译： 逆变器的转换频率随其内部晶体管的跨导而变化，作为温度和偏置电平的函数。 为了保持恒定的跨越温度的转换频率，并且因此降低由逆变器引入的相位噪声变化，系统，方法和电路被公开用于使温度变化电流偏置逆变器，使得晶体管的跨导在温度保持恒定的同时保持 这样做最低的功耗。 各种实施例可以包括使用具有比例绝对温度（PTAT）装置的电流源。

公开(公告)号：US08081039B1

公开(公告)日：2011-12-20

申请号：US12793309

申请日：2010-06-03

申请人： Alessandro Venca ,  Enrico Sacchi ,  Sehat Sutardja

发明人： Alessandro Venca ,  Enrico Sacchi ,  Sehat Sutardja

IPC分类号： H03B5/12

CPC分类号： H03B5/1221 ,  H03B5/1212 ,  H03B5/1228 ,  H03B2200/0062 ,  H03B2200/0064

摘要： In one embodiment, a voltage controlled oscillator (VCO) is provided. The VCO includes a tank circuit. Also, the VCO includes a first pair of transistors. The drains of the first pair of transistors are coupled to the tank circuit and the gates of the first pair of transistors are cross-coupled with the drains of the first pair of transistors. The first pair of transistors each have a first threshold voltage. The VCO further includes a second pair of transistors. The drains of the second pair of transistors are respectively coupled to the sources of the first pair of transistors and the gates of the second pair of transistors are respectively coupled to the gates of the first pair of transistors, The second pair of transistors each have a second threshold voltage higher than the first threshold voltage.

摘要翻译： 在一个实施例中，提供压控振荡器（VCO）。 VCO包括一个储能电路。 而且，VCO包括第一对晶体管。 第一对晶体管的漏极耦合到储能电路，第一对晶体管的栅极与第一对晶体管的漏极交叉耦合。 第一对晶体管每个具有第一阈值电压。 VCO还包括第二对晶体管。 第二对晶体管的漏极分别耦合到第一对晶体管的源极，第二对晶体管的栅极分别耦合到第一对晶体管的栅极。第二对晶体管每个具有 第二阈值电压高于第一阈值电压。

公开(公告)号：US06992367B2

公开(公告)日：2006-01-31

申请号：US10712211

申请日：2003-11-12

申请人： Pietro Erratico ,  Enrico Sacchi ,  Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

发明人： Pietro Erratico ,  Enrico Sacchi ,  Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

IPC分类号： H01L29/00

CPC分类号： B81C1/00404

摘要： The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.

摘要翻译： 该方法包括以下步骤：在半导体材料晶片的顶部上形成具有格子结构的孔掩模，并且包括多个开口，每个开口具有大致正方形的形状，并且相对于平面的平面倾斜45° 晶圆; 在晶片的TMAH中进行各向异性蚀刻，使用所述带孔掩模，从而形成空腔，其横截面具有倒立的等腰梯形的形状; 并且使用TEOS进行化学气相沉积，由此形成TEOS层，其完全封闭了孔罩的开口，并且限定了覆盖在空腔上的隔膜，并且随后可以制造悬浮的一体结构。

公开(公告)号：US08896387B1

公开(公告)日：2014-11-25

申请号：US13330140

申请日：2011-12-19

申请人： Alessandro Venca ,  Enrico Sacchi ,  Sehat Sutardja

发明人： Alessandro Venca ,  Enrico Sacchi ,  Sehat Sutardja

IPC分类号： H03B5/12

CPC分类号： H03B5/1221 ,  H03B5/1212 ,  H03B5/1228 ,  H03B2200/0062 ,  H03B2200/0064

摘要： In one embodiment, a voltage controlled oscillator (VCO) is provided. The VCO includes a tank circuit. Also, the VCO includes a first pair of transistors. The drains of the first pair of transistors are coupled to the tank circuit and the gates of the first pair of transistors are cross-coupled with the drains of the first pair of transistors. The first pair of transistors each have a first threshold voltage. The VCO further includes a second pair of transistors. The drains of the second pair of transistors are respectively coupled to the sources of the first pair of transistors and the gates of the second pair of transistors are respectively coupled to the gates of the first pair of transistors, The second pair of transistors each have a second threshold voltage higher than the first threshold voltage.

摘要翻译： 在一个实施例中，提供压控振荡器（VCO）。 VCO包括一个储能电路。 此外，VCO包括第一对晶体管。 第一对晶体管的漏极耦合到储能电路，第一对晶体管的栅极与第一对晶体管的漏极交叉耦合。 第一对晶体管每个具有第一阈值电压。 VCO还包括第二对晶体管。 第二对晶体管的漏极分别耦合到第一对晶体管的源极，第二对晶体管的栅极分别耦合到第一对晶体管的栅极。第二对晶体管每个具有 第二阈值电压高于第一阈值电压。

公开(公告)号：US06693039B2

公开(公告)日：2004-02-17

申请号：US09797206

申请日：2001-02-27

申请人： Pietro Erratico ,  Enrico Sacchi ,  Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

发明人： Pietro Erratico ,  Enrico Sacchi ,  Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

IPC分类号： H01L21302

CPC分类号： B81C1/00404

摘要： The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.